Path: csiph.com!eternal-september.org!feeder.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Paul Rubin Newsgroups: comp.lang.forth Subject: Re: Stack Sizes Date: Mon, 03 Oct 2016 16:28:28 -0700 Organization: A noiseless patient Spider Lines: 32 Message-ID: <87twctxbab.fsf@nightsong.com> References: <5d771b3c-0099-43eb-9373-c25f0d40e843@googlegroups.com> Mime-Version: 1.0 Content-Type: text/plain Injection-Info: mx02.eternal-september.org; posting-host="590ea01354cf4bcbcd857d7ebbd88128"; logging-data="5976"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+EC0KRGpTFSofgZStSG5Po" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Cancel-Lock: sha1:Ld56meefhm7RFXWIfepo+bjOG2I= sha1:2RjAAE7AyhfJuYdBZzJpDmp2c2I= Xref: csiph.com comp.lang.forth:51588 Walter Banks writes: > I guess what is modest hardware size. How big is needed to accommodate > most applications given that a user or compiler makes a reasonable > attempt to write good code. What do you mean by "most applications"? Applications that run on workstations, mobile phones, internet servers etc. usually consume far more resources than the applications that run on stack processors from the Forth world. Large Forth applications (there are a few) usually run on large machines (PC's etc.) so maybe aren't relevant to your question. Forth programs on stack machines or microcontrollers generally avoid complicated control flow and tend to use between a few and some dozens of stack cells, plus up to a few K of memory cells. The GA144 cpus iirc have 10 data stack levels (T and S registers plus an 8-level circular buffer) and 9 return stack levels (R register plus 8-level circular buffer) but they are very small cpus. The Novix used off-chip stack memory with 256 elements for each stack, plus a few on-chip registers for the top levels. The J1 appears to have 32 levels for each stack: http://excamera.com/sphinx/fpga-j1.html If you can say the application area your processor is targeted at, you might get better advice. If it's a general purpose processor that has to run mainstream software, you probably want a conventional architecture. The main reason other than recreation I can think of to make a stack CPU is you want some tiny sequencer in a little corner of a bigger FPGA application. In that case you probably want to size the CPU to handle the surrounding application's specific requirements. In the designs I've seen, you can choose the stack size by changing a couple lines of Verilog.