Path: csiph.com!eternal-september.org!feeder.eternal-september.org!nntp.eternal-september.org!.POSTED!not-for-mail From: Kragen Javier Sitaker Newsgroups: comp.lang.forth,comp.arch Subject: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Date: Tue, 01 Sep 2026 17:15:12 -0300 Organization: Primarily biological and memetic Lines: 20 Message-ID: <87a4q0afu7.fsf_-_@debian> References: <87qzk0nejz.fsf@nightsong.com> <116d89d$27baf$1@paganini.bofh.team> <2026Aug24.095510@mips.complang.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Injection-Date: Tue, 01 Sep 2026 20:17:31 +0000 (UTC) Injection-Info: dont-email.me; logging-data="2270750"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19X7UVWe9JvB2Se4DPjekgA"; posting-host="fa8aa933a678f631da317852f835fb16" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) Cancel-Lock: sha1:9wDZw9MOToW8V6ut9iEKokTeY5M= sha1:z6NIuyaIwz5YBxnkCkh4Y3q+uWw= sha256:8ZDakB4IplHtRjE2cng3pD7CXtzVMnv0Xx3UmHGmcj4= sha1:abjmpo3KzRFU+1dNp0JSsGTClHA= sha256:NJpRGOGEkkLh21UMVvv9dhGN8c+h/UKEBX3xhBReT94= Xref: csiph.com comp.lang.forth:135511 comp.arch:117720 anton@mips.complang.tuwien.ac.at (Anton Ertl) writes: > RISC-V follows its ancestor MIPS (from where it also has many > mnemonics) in this respect. For a new way to add the carry > functionality without adding a condition code register, read > > https://www.complang.tuwien.ac.at/anton/tmp/carry.pdf > > (unpublished). This is a fascinating idea. I guess the MuP21 had a carry bit in every “general-purpose register”, making them 21 bits, but I’ve never seen any other architecture do this, nor a version that separates out overflow bits from carry bits. I also didn’t realize that (base) RISC-V needed 5 instructions *per word* for multi-precision addition. Thank you for sharing your draft! Kragen