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From: Rod Pemberton <NeedNotReplyHere@xrsevnneqk.cem>
Newsgroups: comp.lang.forth
Subject: Re: Are stack machines inherently faster?
Date: Sun, 4 Dec 2016 10:10:11 -0500
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On Sun, 04 Dec 2016 03:41:07 -0600
Andrew Haley <andrew29@littlepinkcloud.invalid> wrote:

> Rod Pemberton <NeedNotReplyHere@xrsevnneqk.cem> wrote:
> > On Sat, 3 Dec 2016 17:15:42 -0800 (PST)
> > hughaguilar96@gmail.com wrote:
> >   
> >> 2.) Registers are very expensive in terms of hardware resources, so
> >> you can't have a lot.  
> > 
> > Why?
> > 
> > Modern processors have large caches and multiple layers of them.
> > There is no reason that a register file can't be just as large.  
> 
> https://lh3.googleusercontent.com/-Um9o8x0OulQ/VoFj0Mq2MqI/AAAAAAAAyPk/2twW9hihUvw/w500/chip-labeled.png
> 
> It's quite impressive to look at the sheer size of the register file
> in a simple processor like the ARM1.  The reason for this is that
> registers have to be very fast (so need big transistors to drive the
> lines) and they need to be multi-ported.  Seen here, the register file
> (only 16 registers) is twice the size of the ALU.  Caches can be made
> much smaller because they don't have to be anything like as fast and
> don't have to read or write many operands in a cycle.
> 

http://www.chip-architect.com/news/Real_Sao_Paolo_Shanghai_Nehalem_1600x784_.jpg
https://randomascii.files.wordpress.com/2012/12/image1.png

It appears to me that the caches can consume far more area than any
other logic block.  The blocks within the processor cores - one of
which should be the register file - are far smaller than labeled caches.
The processor in second image (Sandybridge) seems to have integrated the
L1 and L2 caches into the cores, at least based on how they're labeled.


Rod Pemberton