Path: csiph.com!usenet.pasdenom.info!weretis.net!feeder1.news.weretis.net!feeder.erje.net!border3.nntp.ams.giganews.com!Xl.tags.giganews.com!border1.nntp.ams.giganews.com!nntp.giganews.com!local2.nntp.ams.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Mon, 08 Oct 2012 14:56:03 -0500 From: Chris Hinsley Newsgroups: comp.lang.forth Date: Mon, 8 Oct 2012 20:56:03 +0100 Message-ID: <2012100820560326642-chrishinsley@gmailcom> References: <76fe0697-97b3-4844-9b18-b2b86e028d8c@googlegroups.com> <971ca4fc-0ec5-457b-b941-c268c2cc48fe@z8g2000yql.googlegroups.com> <2012100820430026080-chrishinsley@gmailcom> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: Your next supercomputer! Just $99 for 16 ARM cores on a chip. (link supplied) User-Agent: Unison/2.1.9 Lines: 52 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-ZlTWsuvqsMIdTzWhjXxoA25mSckLEIqN/2TcZUTrmfDZCe2s7ARbhpata1FrkCNh4hzWy/QbCkljG4s!qlt47tFuclF6D+ezgtU6DVojbg8ldp4JfGw29Rd/JJAvp5qC9LsOhw9sZlHYdyq3K9U= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 3550 Xref: csiph.com comp.lang.forth:16063 On 2012-10-08 19:43:00 +0000, Chris Hinsley said: > On 2012-10-08 08:38:34 +0000, Mark Wills said: > >> "The secret sauce in the Epiphany design is the memory architecture, >> which allows any core to access the SRAM of any other core on the die. >> This SRAM is mapped as a single address space across the cores, >> greatly simplifying memory management. Each core has a direct memory >> access (DMA) unit that can prefetch data from external flash memory." >> >> Oh. That is seriously nice. >> >> See here: >> http://www.theregister.co.uk/2012/10/07/adapteva_epiphany_parallel_computing_kickstarter/ >> > > The hardware and SDK refernce manuals are avaiable for download now > BTW. Check the kickstarter announcement, it has the links to download. > > Wish it had a bit more local memory, but yep, it looks quite nice. > > Chris Actually the memory architecture is very nice, you can even run instructions from the memory of external cores. Esentially the memory address top 6 bits are an core (x,y) address, the lower bits the dram address. The scoreboarding of registers in the dependancy logic can cope fine with instructions and register reads/writes from/to external core addresses. Each hop of a core adds 1 cycle to the stall if you try to use a register prior to the data being available. You can think of the mesh network as 3 seperate 2D token rings, a core can fill in an empty slot as it goes by etc (arbitration logic round robbins the slots between CPU, DMA and the neibouring cores). 2 DMA channels per core that can read/write 2D memory regions, plus chained DMA descriptors so you can do nice Amiga style DMA blit lists etc. Plus I belive the DMA can do remote read/writes, so you can get a cores DMA engine to do transfers from a remote core to another remote core… The 32KB SRAM is organised as 4 8KB banks, each can be accsessed every cycle by various bits of the hardware, instruction read, DMA, etc etc. You need to keep instructions, data in, data out, buffers in seperate banks to hit maximum speed. Probably best for compute kernels ATM till more local memory is available, but there is room in the memory map for more per core ! Bring on the version with 64 cores and 1MB SRAM per core and things will get very interesting ! Chris