Path: csiph.com!xmission!news.snarked.org!border2.nntp.dca1.giganews.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.iecc.com!.POSTED.news.iecc.com!nerds-end From: Hans-Peter Diettrich Newsgroups: comp.compilers Subject: Re: Opcode handler dispatch in an interpreter: Implementing switch on OpCode. Date: Wed, 11 Oct 2017 18:12:33 -0400 (EDT) Organization: Compilers Central Lines: 29 Sender: news@iecc.com Approved: comp.compilers@iecc.com Message-ID: <17-10-020@comp.compilers> References: <17-10-001@comp.compilers> <17-10-004@comp.compilers> <17-10-009@comp.compilers> <17-10-011@comp.compilers> <17-10-014@comp.compilers> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: gal.iecc.com; posting-host="news.iecc.com:2001:470:1f07:1126:0:676f:7373:6970"; logging-data="49748"; mail-complaints-to="abuse@iecc.com" Keywords: optimize, code Posted-Date: 11 Oct 2017 18:12:33 EDT X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:1930 Am 08.10.2017 um 20:36 schrieb George Neuner: > Some of the things to come out of the discussions in c.l.a.x86 were > that the fastest [simple] JIT sequence for an interpreter is a list of > explicit call instructions: e.g., > > call > call > : > > rather than a list of function addresses with a dispatcher. This is > because the call leverages the CPU branch predictor rather than > fighting with it. I'm not sure about a single common instruction cache and branch prediction architecture, the behaviour may differ amongst architectures. The memory bus interface instead should be similar in all architectures, so that it should speed up execution if function code is aligned to the machine's data bus width (size of a chache line). This will make available the highest possible number of sequential instructions after the first read at a non-sequential (jump/call) address. Tail threading instead can benefit from micro code, if that instruction sequence can be implemented in a single dedicated micro code sequence. Again this behaviour depends heavily on the particular machine architecture. Perhaps more instruction sequences in the emulator code can be optimized this way? DoDi