Path: csiph.com!newsfeed.hal-mli.net!feeder3.hal-mli.net!news.misty.com!news.iecc.com!.POSTED!nerds-end From: "Derek M. Jones" Newsgroups: comp.compilers Subject: Re: optimizing compilers for low power design Date: Mon, 16 Jun 2014 12:11:32 +0100 Organization: virginmedia.com Lines: 16 Sender: news@iecc.com Approved: comp.compilers@iecc.com Message-ID: <14-06-008@comp.compilers> References: <14-06-003@comp.compilers> <14-06-004@comp.compilers> NNTP-Posting-Host: news.iecc.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Trace: miucha.iecc.com 1402934142 58546 2001:470:1f07:1126:0:676f:7373:6970 (16 Jun 2014 15:55:42 GMT) X-Complaints-To: abuse@iecc.com NNTP-Posting-Date: Mon, 16 Jun 2014 15:55:42 +0000 (UTC) Keywords: optimize, architecture, comment Posted-Date: 16 Jun 2014 11:55:42 EDT X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:1263 Kaz, > Furthermore, even if power cost is real, and you choose instructions according > to power cost, it's not going to work because instructions have to be primarily > chosen according to the computation that needs to be done. There has been some interesting work on making power minimization a constraint during instruction scheduling. A surprising percentage of power is consumed when a signal changes from 0 to 1 or from 1 to 0. So the idea is to arrange instruction order to minimise the number of transitions at each bit position in an instruction sequence. [CMOS only uses power when it switches, so I'd think approximately all of the power would be consumed when a signal changes. The idea of Gray coded instruction streams is weirdly appealing. -John]