Path: csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!nx02.iad01.newshosting.com!newshosting.com!69.16.185.11.MISMATCH!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!news.iecc.com!.POSTED!nerds-end From: George Neuner Newsgroups: comp.compilers Subject: Re: Green Compiler ? Date: Mon, 31 Dec 2012 01:24:13 -0500 Organization: A noiseless patient Spider Lines: 32 Sender: johnl@iecc.com Approved: comp.compilers@iecc.com Message-ID: <13-01-002@comp.compilers> References: <12-12-010@comp.compilers> <12-12-012@comp.compilers> <12-12-022@comp.compilers> <12-12-028@comp.compilers> <12-12-034@comp.compilers> <12-12-037@comp.compilers> NNTP-Posting-Host: news.iecc.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: leila.iecc.com 1357091644 21497 64.57.183.58 (2 Jan 2013 01:54:04 GMT) X-Complaints-To: abuse@iecc.com NNTP-Posting-Date: Wed, 2 Jan 2013 01:54:04 +0000 (UTC) Keywords: performance, architecture Posted-Date: 01 Jan 2013 20:54:04 EST X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com X-Received-Bytes: 2453 Xref: csiph.com comp.compilers:825 On Sun, 30 Dec 2012 08:14:26 +0100, Hans-Peter Diettrich wrote: >Peter Dassow schrieb: >> On 28.12.2012 08:35, Hans-Peter Diettrich wrote: >>> >>> Please note that most CMOS processor power consumption results from >>> switching (stray) capacities, and only a small percentage for leak >>> currents. E.g. a register or gate consumes such power whenever a bit is >>> changed, and almost nothing when it has reached an stable state. Smaller transistors have more leakage. >> So using extensively registers instead of "conventional" memory (e.g. >> DDR-RAM, memory outside a CPU) will save energy (if equal functionality >> is given) ? > >I don't see a relationship here, except that external memory is slow >and [in x86] a couple of caches and address translations are involved >in reading from RAM. But associative cache and external memory accesses both are power intensive. >But registers are a very scarce resource, so that frequent loading from >memory is hardly avoidable. My opinions are colored by experience with DSPs, but I have long thought that it would be helpful to have a few K-words of non-cache scratchpad memory very close (1..2 cycles) to the CPU. George