Path: csiph.com!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!news.misty.com!news.iecc.com!.POSTED!nerds-end From: Hans-Peter Diettrich Newsgroups: comp.compilers Subject: Re: Green Compiler ? Date: Sun, 30 Dec 2012 08:14:26 +0100 Organization: Compilers Central Lines: 24 Sender: johnl@iecc.com Approved: comp.compilers@iecc.com Message-ID: <12-12-037@comp.compilers> References: <12-12-010@comp.compilers> <12-12-012@comp.compilers> <12-12-022@comp.compilers> <12-12-028@comp.compilers> <12-12-034@comp.compilers> NNTP-Posting-Host: news.iecc.com Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-Trace: leila.iecc.com 1356903501 42127 64.57.183.58 (30 Dec 2012 21:38:21 GMT) X-Complaints-To: abuse@iecc.com NNTP-Posting-Date: Sun, 30 Dec 2012 21:38:21 +0000 (UTC) Keywords: code, performance Posted-Date: 30 Dec 2012 16:38:21 EST X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:821 Peter Dassow schrieb: > On 28.12.2012 08:35, Hans-Peter Diettrich wrote: >> >> Please note that most CMOS processor power consumption results from >> switching (stray) capacities, and only a small percentage for leak >> currents. E.g. a register or gate consumes such power whenever a bit is >> changed, and almost nothing when it has reached an stable state. >> > So using extensively registers instead of "conventional" memory (e.g. > DDR-RAM, memory outside a CPU) will save energy (if equal functionality > is given) ? I don't see a relationship here, except that external memory is slow and [in x86] a couple of caches and address translations are involved in reading from RAM. But registers are a very scarce resource, so that frequent loading from memory is hardly avoidable. Register usage is already optimized by every (good) compiler, reducing runtime and power consuption at the same time. This was a very narrow bottleneck of the IA-32 architecture, until the 64 bit (AMD) model increased the number of registers considerably (16 addressable, of 128 [256?] shadow registers). The CPU computation circuitry and usage is the same, regardless of the operand sources. DoDi