Path: csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!usenet.stanford.edu!news.iecc.com!.POSTED!nerds-end From: Walter Banks Newsgroups: comp.compilers Subject: Re: Green Compiler ? Date: Fri, 28 Dec 2012 10:42:47 -0500 Organization: Aioe.org NNTP Server Lines: 40 Sender: johnl@iecc.com Approved: comp.compilers@iecc.com Message-ID: <12-12-030@comp.compilers> References: <12-12-010@comp.compilers> NNTP-Posting-Host: news.iecc.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Trace: leila.iecc.com 1356817811 94125 64.57.183.58 (29 Dec 2012 21:50:11 GMT) X-Complaints-To: abuse@iecc.com NNTP-Posting-Date: Sat, 29 Dec 2012 21:50:11 +0000 (UTC) Keywords: design, performance Posted-Date: 29 Dec 2012 16:50:11 EST X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:814 Abid wrote: > Hi: > > It seems that the Power Wall is becoming a major issue, especially for High > Performance Computing. Current compilers work has two dimensional model, i.e., > all the optimization phases are targeted either towards reducing execution > time or code size. My question is: Do we need to change this model and make it > three dimensional by adding power axis in the search space? If yes, then we > have to revisit all the phases and adjust them or come up with new cost > models for these phases. > > I will be grateful if some one can point me to the latest efforts/projects > with respect to power efficient compilation for high performance computing. There has been a lot of work on energy efficient compiling. In the 80's were were working on a data logging project where the devices needed to run on battery power unattended for for more than a year in very bad environments. We created a compiler (CMOS variant to the Motorola 6805) to do the development work initially optimized to require minimum execution cycles. As the project evolved we refined our model of the power profile of the processor and made design modifications to product to reduce energy consumption. Our models started to look at both number of RAM and ROM fetches and RAM writes as well as cycle counts. RAM and ROM access were separately characterized. We focused on utilizing page0 zero memory accesses and switching external memory from sleep to active mode and minimizing the time each memory was active. The accumulation of the various optimizations made a big difference to the energy consumption of the application. Walter Banks