Path: csiph.com!eternal-september.org!feeder3.eternal-september.org!news.eternal-september.org!eternal-september.org!.POSTED!not-for-mail From: Lynn Wheeler Newsgroups: comp.arch Subject: Re: Why VAX Was the Ultimate CISC and Not RISC Date: Sat, 01 Mar 2025 18:29:50 -1000 Organization: Wheeler&Wheeler Lines: 97 Message-ID: <871pvgukap.fsf@localhost> References: <2025Mar1.125817@mips.complang.tuwien.ac.at> <2025Mar1.232526@mips.complang.tuwien.ac.at> MIME-Version: 1.0 Content-Type: text/plain Injection-Date: Sun, 02 Mar 2025 05:29:58 +0100 (CET) Injection-Info: dont-email.me; posting-host="d32d00b3e97878e2260d26fd5b2dc4c2"; logging-data="683042"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+7wA/iktm4xnDAvFB6dJ5o8o3uBu9fyk8=" User-Agent: Gnus/5.13 (Gnus v5.13) Cancel-Lock: sha1:NBB5T3X+SL6wkMHhO61kFeQlG4w= sha1:bZqfp9fiiMQOTbo7PV4i2eBaAN4= Xref: csiph.com comp.arch:110893 anton@mips.complang.tuwien.ac.at (Anton Ertl) writes: > IBM tried to commercialize it in the ROMP in the IBM RT PC; Wikipedia > says: "The architectural work on the ROMP began in late spring of > 1977, as a spin-off of IBM Research's 801 RISC processor ... The first > examples became available in 1981, and it was first used commercially > in the IBM RT PC announced in January 1986. ... The delay between the > completion of the ROMP design, and introduction of the RT PC was > caused by overly ambitious software plans for the RT PC and its > operating system (OS)." And IBM then designed a new RISC, the > RS/6000, which was released in 1990. ROMP originally for DISPLAYWRITER follow-on ... running CP.r operating system and PL.8 programming language. ROMP was minimal 801, didn't have supervisor/problem mode ... at the time their claim was PL.8 would only generate correct code and CP.r would only load/execute correct programs. They claimed 40bit addressing ... 32 bit addresses ... but top four bits selected 16 "segment registers" that contained 12bit segment-identifiers. ... aka 28bit segment displacement and 12bit segment-ids (40bits) .... and any inline code could change segment register value ... as easily as could load any general register. When follow-on to DISPLAYWRITER was canceled, they pivoted to UNIX workstation market and got the company that had done AT&T unix port to IBM/PC for PC/IX ... to do AIX. Now ROMP needed supervisor/problem mode and inline code could no longer change segment register values ... needed to have supervisor call. Folklore is they also had 200 PL.8 programmers and needed something for them to do, so they gen'ed a abstract virtual machine system ("VRM") (implemented in PL.8) and had AIX port be done to the abstract virtual machine definition (instead of real hardware) .... claiming that the combined effort would be less (total effort) than having the outside company do the AIX port to the real hardware (also putting in a lot of IBM SNA communication support). The IBM Palo Alto group had been working on UCB BSD port to 370, but was redirected to do it instead to bare ROMP hardware ... doing it in enormously significantly less resources than the VRM+AIX+SNA effort. Move to RS/6000 & RIOS (large multi-chip) doubled the 12bit segment-id to 24bit segment-id (and some left-over description talked about it being 52bit addressing) and eliminated the VRM ... and adding in some amount of BSDisms. AWD had done their own cards for PC/RT (16bit AT) bus, including a 4mbit token-ring card. Then for RS/6000 microchannel, AWD was told they couldn't do their own card, but had to do PS2 microchannel cards. The communication group was fiercely fighting off client/server and distributed computing and had seriously performance knee-capped PS2 cards, including ($800) 16mbit token-ring card (the PS2 microchannel which had lower card throughput than the PC/RT 4mbit TR card). There was joke that PC/RT 4mbit TR server having higher throughput than RS/6000 16mbit TR server. There was also joke that the RS6000/730 with VMEbus was a work around corporate politics and being able to install high-performance workstation cards We got the HA/6000 project in 1988 (approved by Nick Donofrio), originally for NYTimes to move their newspaper system off VAXCluster to RS/6000. I rename it HA/CMP. https://en.wikipedia.org/wiki/IBM_High_Availability_Cluster_Multiprocessing when I start doing technical/scientific cluster scale-up with national labs (LLNL, LANL, NCAR, etc) and commercial cluster scale-up with RDBMS vendors (Oracle, Sybase, Ingres, Informix that had vaxcluster support in same source base with unix). The S/88 product administrator then starts taking us around to their customers and also has me do a section for the corporate continuous availability strategy document ... it gets pulled when both Rochester/AS400 and POK/(high-end mainframe) complain they couldn't meet the requirements. Early Jan1992 have a meeting with Oracle CEO and IBM/AWD Hester tells Ellison we would have 16-system clusters by mid92 and 128-system clusters by ye92. Then late Jan92, cluster scale-up is transferred for announce as IBM Supercomputer (for technical/scientific *ONLY*) and we are told we can't work on anything with more than four processors (we leave IBM a few months later). Contributing was the mainframe DB2 DBMS group were complaining if we were allowed to coninue, it would be at least five years ahead of them. Neither ROMP or RIOS supported bus/cache consistency for multiprocessor operation. The executive we reported to, went over to head up ("AIM" - Apple, IBM, Motorola) Somerset for single chip 801/risc ... but also adopts Motorola 88k bus enabling multiprocessor configurations. He later leaves Somerset for president of (SGI owned) MIPS. trivia: I also had HSDT project (started in early 80s), T1 and faster computer links, both terrestrial and satellite ... which included custom designed TDMA satellite system done on the other side of the pacific ... and put in 3-node system. two 4.5M dishes, one in San Jose and one in Yorktown Research (hdqtrs, east coast) and a 7M dish in Austin (where much of the RIOS design was going on). San Jose also got an EVE, a superfast hardware VLSI logic simulator (scores of times faster than existing simultion) ... and it was claimed that Austin being able to use the EVE in San Jose, helped bring RIOS in a year early. -- virtualization experience starting Jan1968, online at home since Mar1970