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From: Tim Rentsch <tr.17687@z991.linuxsc.com>
Newsgroups: comp.arch
Subject: Re: endian history
Date: Fri, 02 Oct 2026 21:31:26 -0700
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Michael S <already5chosen@yahoo.com> writes:

> On Thu, 01 Oct 2026 09:15:29 -0700
> Tim Rentsch <tr.17687@z991.linuxsc.com> wrote:
>
>> anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>
>>> Tim Rentsch <tr.17687@z991.linuxsc.com> writes:
>>>
>>>>> With wrapping signed arithmetic, all of the semantics of
>>>>> unsigned arithmetic is the same, except for right shift and
>>>>> division operations.
>>>>
>>>> Also left shift
>>>
>>> No.  The funny thing is that AMD64 has both SHL and SAL
>>> mnemonics, but they encode the same opcodes.  E.g.:
>>>
>>> D3 /4 	SAL r/m32, CL
>>> D3 /4 	SHL r/m32, CL
>>
>> That may be true for AMD64.  It is not true for other
>> two's complement architectures.
>
> I would think that it is true on all twoc architectures that don't
> trap on signed integer overflow.

Did you embark on any research to reach this characterization, or
is it just speculation?

> Also it is a defenition guaranteed on all supported targets by gcc.

I don't know what that has to do with the question here, which is
more about machine architectures and/or Java, and at first blush
has nothing to do with gcc.