X-FeedAbuse: http://nntpfeed.proxad.net/abuse.pl feeded by 88.191.16.109 Path: csiph.com!x330-a1.tempe.blueboxinc.net!usenet.pasdenom.info!news.dougwise.org!nntpfeed.proxad.net!nospam.fr.eu.org!usenet-fr.net!de-l.enfer-du-nord.net!feeder2.enfer-du-nord.net!news.glorb.com!news-xfer.nntp.sonic.net!posts.news.sonic.net!nnrp1.nntp.sonic.net!not-for-mail Message-ID: <4E57332F.3050600@bitblocks.com> Date: Thu, 25 Aug 2011 22:46:23 -0700 From: Bakul Shah User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.7; en-US; rv:1.9.2.20) Gecko/20110804 Lightning/1.0b2 Thunderbird/3.1.12 MIME-Version: 1.0 Newsgroups: comp.arch Subject: Re: indexing register References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Lines: 64 Organization: Sonic.Net NNTP-Posting-Date: 26 Aug 2011 05:46:23 GMT NNTP-Posting-Host: 3010f087.news.sonic.net X-Trace: DXC=1j@eaTLMfYiaRW0U39Kc?dm4K\QM1CV^`1OYf0H`?;Xa^>0m69XVa:oU[Zjk:d[l;fdIJ\kB<^Z^n X-Complaints-To: abuse@sonic.net Xref: x330-a1.tempe.blueboxinc.net comp.arch:3145 On 8/24/11 12:36 PM, Joe Keane wrote: > This is bouncing around my head. > > Say we have a machine with a lot of general registers, at least 1024 and > possibly much more. [There's some VLIWy stuff, but i think it's > irrelevant, so pretend i tell you it's a standard RISCy machine.] > > We add a register BL (base latch). > > Every op that get/put a register has a bit called 'index'. If off, the > register number is in the op; if on, we add that to BL to get the correct > register number. Now we can cheat a bit on the register field; maybe > the machine has 16384 registers, but we can only access 512 without > changing BL. AMD29k did this. Most instructions were of the form C = A op B Where A, B & C were each 1 bit (same as your index) + 7 bit reg #. If the top bit was off, you directly accessed reg1..reg127 from the register file. If it was on, you add the 7 bit reg# to reg1 and used the lowest 7 bits to index the other 128 registers from the 256 register file. So reg1 (called gr1) was the same as your BL but only for 128 registers. reg# 0 was special. Depending on whether it was in the A, B or C field, you picked up the real reg# from `special' registers IPA, IPB or IPC and accessed that. > It's unclear whether access to BL is a KISS movtcr/movfcr, or we should > have some ops like save/restore. It is tempting, we can put an adder > next to BL and he won't need to bother anyone. In either case we also > want a compare with some bound; if out of whack, do something-or-other. This limit checking was done on function entry or exit. If the function wanted N registers and the file has < N, you took a trap, saved some register contents to memory and returned. Similar on function exit (if the caller's registers were in memory, you took a trap and restored them). > Basically register windows, but each op can choose to index or not. > > Really, there's BL1 and BL2, and of course some way to switch between > them. [Oh and you can't use it in the next instruction, the rule for > everything.] Presumably it's not useful to let each op select. Or > maybe three (ABL/FBL/SBL stolen from the VAX). gr1 was used as a stack ptr and you adjusted it twice in a function (except leaf functions). So don't see the need for two such registers. > Comments welcome on how this is useful, or it allows neat tricks. Is > there a reason to have more than two? Also comparison with existing... 29k was a fun processor to program! Not sure how well its 3 ported 256 register file would have scaled in speed. Perhaps modern compilers would have made better use of its huge register set. On the other hand a large register set made context switching between threads expensive. It also needed to maintain a separate memory stack which complicated things. Because of that I felt it would be better to have reg# fields in an instructions reference *memory* relative to a stack ptr. Then stack adjustment could be seen as a hint to move data between the cache and memory (or throw stale data away). And context switching would be very quick. Bakul Shah