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Date: Thu, 12 May 2011 19:32:47 -0700
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Subject: Re: Anyone take a serious look at partitioned register sets?
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On 5/12/2011 8:19 AM, Paul A. Clayton wrote:
> On Thursday, May 12, 2011 12:06:59 AM UTC-4, Brett Davis wrote:
> [snip]
>> Intel does fine with just 2 read ports on the register file,
>> most of the values for 4 way execution come from the forwarding
>> network.

P6 had just 2 read ports on the PRF=ROB+RRRF.  Wmt had full porting.
Nhm had underporting, but I can't say how many ports.

Does Sandybridge still have only 2 ports?

> It seems that the EV8 used a register cache rather than a
> traditional forwarding network.

I did not know this.  Are you sure?  Evidence?

In fact, I thought I was the first guy crazy enough to propose a 
register file cache. In fact, I took grief from many ex DEC Alpha guys 
for it.


>> Which high end CPU archs actually fully port out their register file?
>
> Itanium is one example.  (I would not be surprised if
> at least some of the POWER uarchs used full RF porting,
> but I do not remember reading about such--and the POWER7
> microarchitecture paper is behind a paywall.)

Amusing anecdote: a guy I mentored at AMD told me that he thought that 
he had invented non-fully-ported register files at Sun.  Even though we 
had used them on P6 at Intel (Dave Papworth's great idea), and it was in 
the baseline K10 uarch at AMD.

> I think at least some of the earlier Intel x86 used operand
> capture, in which case forwarding of a result does not have
> to be correspond to immediate issue of the dependent
> operation.  The associated reading of operands at entry to
> issue queue could also provide more flexibility in scheduling
> reads than read operands after scheduling.

The term "operand capture" is a term I invented to describe the P6 CAM 
based RS.  But it also generalizes to non-CAM based OC (Operand Capture) 
mechanisms.