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From: cross@spitfire.i.gajendra.net (Dan Cross)
Newsgroups: comp.arch
Subject: Re: Performance of xchg reg,reg
Date: Sun, 18 Oct 2026 17:47:51 -0000 (UTC)
Organization: PANIX Public Access Internet and UNIX, NYC
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References: <2026Oct13.104347@mips.complang.tuwien.ac.at> <1792257076-5857@newsgrouper.org> <11b0bd3$b5b$1@reader2.panix.com> <nv6BS.146451$4b2.140904@fx47.iad>
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In article <nv6BS.146451$4b2.140904@fx47.iad>,
EricP  <ThatWouldBeTelling@thevillage.com> wrote:
>On 2026-Oct-17 13:31, Dan Cross wrote:
>[snip]
>Intel Volume 3 System Programmers guide 10.1.2 Bus Locking
>10.1.2.1 Automatic Locking is explicit:...
>[snip]

Yes, which in my view, lends more support to requiring that the
sentence in question in the description of the `LOCK` prefix be
read in the context of the overall paragraph, which is clearly
talking about cases where the destination is a memory operand.

Sadly, however, that doesn't make the sentence itself any less
ambiguous, and once you have ambiguity in a technical document
like the SDM, you've got a problem.

Intel can fix this easily by adding another phrase to that last
sentence, ", when the destination is a memory operand."  (Or
words to that effect.)  I'm speculating, but they probably
haven't because it seems rather obvious that that is the intent,
and no one has brought it up as a problem.

	- Dan C.