Path: csiph.com!goblin1!goblin3!goblin.stu.neva.ru!panix!not-for-mail From: Hul Tytus Newsgroups: comp.arch.embedded Subject: Re: Arm registers Date: Fri, 16 Apr 2021 22:12:58 +0000 (UTC) Organization: PANIX Public Access Internet and UNIX, NYC Lines: 41 Message-ID: References: NNTP-Posting-Host: panix2.panix.com X-Trace: reader1.panix.com 1618611178 16221 166.84.1.2 (16 Apr 2021 22:12:58 GMT) X-Complaints-To: abuse@panix.com NNTP-Posting-Date: Fri, 16 Apr 2021 22:12:58 +0000 (UTC) Xref: csiph.com comp.arch.embedded:30454 Richard - you've verified that the v7-m processors use both the 16 bit and the 32 bit instructions and for that I thank you. I'm guessing now the Cortex processors, not the v7-m types, are what I should be looking at. Do you know the title of Arm's Architectural Reference Manual for the Cortex versions? Hul Richard Damon wrote: > On 4/16/21 3:30 PM, Hul Tytus wrote: > > sci.electronics.design > > Arm Cortex assembley code > > > > Does the Arm Cortex support both the "thumb" 16 bit machine codes and also > > the 32 bit codes? I had been under the impression that Cortex devices only > > provided the thumb codes but a little time going through "Arm v7-M > > Architecture Reference Manual" indicates otherwise. Whether or not that > > reference manual is suitable for Cortex information needs verification also. > > There may be a more pertinent text available. > > And another question: the thumb instructions show 8 available registers > > rather than 16. However, somewhere on the internet a site states that 16 > > registers are available & which group of 8 varies with the "processor state". > > Any suggestions on an Arm manual or text that defines "processor state"? The > > CPS (change processor state) machine code description in the "Arm v7-M > > Architecture Reference Manual" doesn't mention register groups. > > > > Hul > > > Thumb instructions can be 16 or 32 bit, the 32 bit instruction are > different than the non-thumb 32-bit mode, which may be the confusion, > and are sometimes called Thumb-2 instructions, as they weren't available > in the first version of the Arm Processors that just had the basic 16 > bit Thumb instructions. > The Arm v7-M processor has 16 32-bit registers, but the top 3 are > special purpose (LR, SP, PC), so only R0-R12 are really general purpose. > Most of the 16-bit thumb instruction can only access R0-R7, (but some > will use the special registers implicitly), to get to the full set of > registers you often need to use a 32-bit Thumb instructions.