Path: csiph.com!eternal-september.org!feeder.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Don Y Newsgroups: comp.arch.embedded Subject: Re: Speaking of Multiprocessing... Date: Thu, 23 Mar 2017 16:26:46 -0700 Organization: A noiseless patient Spider Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Thu, 23 Mar 2017 23:23:56 -0000 (UTC) Injection-Info: mx02.eternal-september.org; posting-host="cb404ee80a6293ce4999858a69f08f0b"; logging-data="31813"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18btSivhV8VQnGdtCootgVZ" User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 In-Reply-To: Cancel-Lock: sha1:J1/W2ZHX66LDvrEYTEmS/EYpbQs= Xref: csiph.com comp.arch.embedded:26182 On 3/23/2017 4:19 PM, Tim Wescott wrote: > On Thu, 23 Mar 2017 18:38:13 -0400, rickman wrote: > >> I recall a discussion about the design of an instruction set >> architecture where someone was saying an instruction was required to >> test and set a bit or word as an atomic operation if it was desired to >> support multiple processors. Is this really true? Is this a function >> that can't be emulated with other operations including the disabling of >> interrupts? > > AFAIK as long as you surround your "test and set" with an interrupt > disable and an interrupt enable then you're OK. At least, you're OK > unless you have a processor that treats interrupts really strangely. Rethink that for the case of SMP... (coincidentally, "Support Multiple Processors" :> )