Path: csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!nntp.club.cc.cmu.edu!micro-heart-of-gold.mit.edu!newsswitch.lcs.mit.edu!nntp.TheWorld.com!.POSTED!not-for-mail From: jhallen@TheWorld.com (Joseph H Allen) Newsgroups: comp.arch.embedded Subject: Re: Open source FPGA toolchain ?, was: Re: Small, fast, resource-rich processor Date: Mon, 30 Sep 2013 20:15:20 +0000 (UTC) Organization: The World : www.TheWorld.com : Since 1989 Lines: 19 Message-ID: References: <7x61tiayp8.fsf@ruckus.brouhaha.com> NNTP-Posting-Host: shell01.theworld.com X-Trace: pcls7.std.com 1380572120 32597 192.74.137.71 (30 Sep 2013 20:15:20 GMT) X-Complaints-To: abuse@TheWorld.com NNTP-Posting-Date: Mon, 30 Sep 2013 20:15:20 +0000 (UTC) X-Newsreader: trn 4.0-test72 (19 April 1999) Xref: csiph.com comp.arch.embedded:14013 In article <7x61tiayp8.fsf@ruckus.brouhaha.com>, Paul Rubin wrote: >Simon Clubley writes: >> It doesn't stop me from looking, asking, and wishing however. :-) >Some of the FPGA bitstream formats have been reverse engineered: a web >search should find some info. There are FOSS place and route tools but >they don't generate bitstreams. Another thing to point out: the place and route tools used by Xilinx and Lattice were developed by NeoCAD- a company which reverse engineered the Xilinx format in ~1991, did a better job than Xilinx's own tools of the time (apr) and got bought by them. -- /* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}