Path: csiph.com!eternal-september.org!feeder.eternal-september.org!nntp.eternal-september.org!.POSTED!not-for-mail From: Lynn Wheeler Newsgroups: alt.folklore.computers Subject: Re: position-independent code (was Re: CMS, Self-hosting and the 6502) Date: Mon, 14 Sep 2026 14:41:47 -1000 Organization: Wheeler&Wheeler Lines: 124 Message-ID: <87o6dz9whg.fsf@localhost> References: <10qehuo$2nu4m$1@dont-email.me> <87h5pqwd5j.fsf@localhost> <10qs7og$129km$4@dont-email.me> <10qt6h6$19mab$1@dont-email.me> <10qucqd$cs9$2@gal.iecc.com> <10qv31u$1l5fk$3@paganini.bofh.team> <10qv7t7$1re07$2@dont-email.me> <10qvlrb$1uf62$2@dont-email.me> <10r0g2r$25l0l$1@dont-email.me> <875x64ugxl.fsf@localhost> <87ld98c634.fsf_-_@debian> <874ifu0x9j.fsf@localhost> <1789284696-4353@newsgrouper.org> MIME-Version: 1.0 Content-Type: text/plain Injection-Date: Tue, 15 Sep 2026 00:41:50 +0000 (UTC) Injection-Info: dont-email.me; logging-data="2138274"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18uOL81U0jj7zJyeqOdzHVReQAQPOWVBkE="; posting-host="1a0413de9a823cec5aea60011456b690" User-Agent: Gnus/5.13 (Gnus v5.13) Cancel-Lock: sha1:vVdpAiHRHyWw36NmO52dHNtmBgk= sha1:PVO2KgZqZldMBXbe/KsHwfQjtVU= sha256:A8NzeJ4w0cOyrShSN1/l3CgmoOsG1ArkE+/Hn+MMe+o= sha1:1fNj19YzwZiwsWISGVyWpsx8bes= sha256:So+Zg8ch2bltSKii8Yx4x/f15OX2umvmkJs6HPvl53k= Xref: csiph.com alt.folklore.computers:235630 James Dow Allen writes: > It was half a century ago that I handled physical TXT card decks. > All my programs were standalone: Slap a "six-card loader" at the front of > the TXT deck, and IPL. > > The source code for my programs always started with > USING *,0 > Did that suppress any RLDs? Don't remember. The six-card loader ignored > RLDs anyway. Actually -- never one to overlook a pointless micro- > optimization -- I "optimized" down to a three-card loader, good enough if > the TXT deck had no REP (hexadecimal patch) cards. I had taken two credit hr intro to Fortran/Computers. At the end of semester was hired to rewrite 1401 MPIO in 360 assembler for 360/30 (64kbyte memory and 2311s). Univ was getting 360/67 for tss/360 replacing 709/1401 (709 tape->tape, 1401 unit record frontend) and got 360/30 temporarily replacing 1401 pending arrival of 360/67. The univ. shutdown the datacenter on weekends and I would have the place dedicated. They gave a bunch of hardware and software manuals and I got to design and implement my own monitor, device drivers, interrupt handlers, storage management, error recovery, etc ... and within a few weeks I had a 2000 card assembler program. I didn't know about rep cards, so learned to read TXT deck cards, duplicate cards, and multi-punch hex patches. Univ. 360/67 arrived within year of taking intro class and I was hired fulltime responsible for OS/360 (768kbte memory and 2314s; TSS/360 not coming to production, so ran as 360/65). 709 did student fortran in less than second. 360/67 (as 360/65) os/360 (MFT9.5) took over a minute, I install HASP cutting time in half. MFT11, I start redoing SYSGEN STAGE2 to carefully place datasets and PDS members to optimize arm seek and (PDS directory) multi-track search, cutting another 2/3rds to 12.9secs. OS/360 never got better than 709 until I install Univ Waterloo WATFOR; as 360/65, WATFOR clocked at 20,000 statements/min (333 statements/sec), student fortran tended to run 30-60 statements. Then IBM CSC came out to install (virtual machine, precursor to vm370) CP/67 (3rd after CSC itself and MIT Lincoln Labs) and I mostly get to play with it during my weekend 48hr window. I then spend a few months rewriting pathlengths for running OS/360 in virtual machine. Source was in OS/360 files which had to be modified, assembled, mark txt deck and merge it into a tray of txt decks (that was CP67 executable). BPS loader IPL the tray of TXT decks which then writes core image to disk, for ipl'ing the system. Bare machine test ran 322secs ... initially 856secs (CP67 CPU 534secs). After a few months I had CP67 CPU down from 534secs to 113secs. I then start rewriting the dispatcher/scheduler , (dynamic adaptive resource manager/default fair share scheduling policy), paging, adding ordered seek queuing (from FIFO) and mutli-page transfer channel programs (from FIFO and optimized for transfers/revolution, getting 2301 paging drum from 70-80 4k transfers/sec to channel transfer peak of 270). Six months after univ initial CP/67 install, CSC was giving one week class in LA. I arrive on Sunday afternoon and asked to teach the class, it turns out that the people that were going to teach it had resigned the Friday before to join one of the 60s CSC CP67 online commercial spin-offs (one offered Mathematica RAMIS, when RAMIS was also offered to TYMSHARE, they did Nomad, then some former Mathematica do FOCUS at Information Builders) Before I graduate, I'm hired fulltime into small group in Boeing CFO office to help with formation of Boeing Computer Services (consolidate all dataprocessing into independent business unit). I think Renton, largest datacenter in the world, 360/65s arriving faster than they could be installed, boxes constantly staged in hallways around machine room (did have lone 360/75, when doing classified work; black rope around area, guards at corners, heavy black felt covering console lights and visible 1403 printer areas). Lots of politics between Renton director and CFO, who only had a 360/30 up at Boeing Field for payroll, although they enlarge the room to install 360/67 for me to play with when I wasn't doing other stuff. I had mid-level management badge so could park in lots closer to the bldgs. 747-3 was flying skies of Seattle getting FAA flt certification. Tours of mock-up of 747 cabin just south of Boeing field would claim 747s carried so many passengers, they would never be serviced with fewer than four jetways. Both Boeing and IBM told stories about 360 announcement day, Boeing submitted an order making the IBM marketing rep, highest paid IBM employee that year. Sales were still straight commission; IBM shifts to quota the following year. At Boeing I modified CP67 to support portions as pageable kernel. Problem was adding more CSECTs (dividing pageable kernel into 4k segments). Problem was I ran into BPS loader had 255 csect limit ... and I was constantly doing hacks to keep the pageable kernel within 255 limit. When I graduated, I joined CSC (instead of staying with Boeing CFO) and one of my hobbies was enhanced production operating systems for internal datacenters (one of the first was the branch office online sales&marketing support HONE was one of the 1st & long time customers). CSC had several card drawer cabinets up on the 9th flr attic ... and prowling through them found source for BPS loader, and modified it to double the maximem csects ... greatly simplifying pageable kernel (wasn't released to customers, but picked up for VM370 follow-on). Co-worker was responsible for CP67-based scientific centers wide-area network. He had three "PUNCH" statements at front of the network assembler source ... that punched hex for a 3card loader. This morphs into the internal corporate network (larger than arpanet/internet from the beginning until sometime mid/late 80s, about the time it was forced to convert to SNA/VTAM). Some of the MIT CTSS/7094 had gone to the 5th flr to do MULTICS and others went to the scientific center on the 4th flr and done virtual machines, networking, invented GML 1969 (morphs into SGML a decade later, after another decade morphs into HTML at CERN), etc Looking at what they were doing for MULTICS on the 5th flr, I created page-mapped filesystem for CP67/CMS ... want to be able to just map virtual memory addresses to pages on disk (w/o having to preload them for the loader could modify the addresses) and support location independent R/O shared (executable) files ... which I later migrate to VM370/CMS. For VM370R3, there is a very small subset released as DCSS, extending shared segment to more than kernel supported with more than just the IPL command. -- virtualization experience starting Jan1968, online at home since Mar1970