Path: csiph.com!eternal-september.org!feeder.eternal-september.org!nntp.eternal-september.org!.POSTED!not-for-mail From: Lynn Wheeler Newsgroups: alt.folklore.computers Subject: Re: compilers and architecture, Just How Bad Was The Intel IAPX432? Date: Sun, 31 May 2026 13:52:34 -1000 Organization: Wheeler&Wheeler Lines: 157 Message-ID: <87ldczf871.fsf@localhost> References: <10ve2mc$m8n2$1@dont-email.me> <10veufm$to3f$1@dont-email.me> <10vfdgs$1vl7$1@gal.iecc.com> MIME-Version: 1.0 Content-Type: text/plain Injection-Date: Sun, 31 May 2026 23:52:38 +0000 (UTC) Injection-Info: dont-email.me; logging-data="1982877"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19FcLIK9V4pAk4+WVFAoQZRT6YZuzbxXcs="; posting-host="13e40a5d9598cce47dc178d1a9d66b3c" User-Agent: Gnus/5.13 (Gnus v5.13) Cancel-Lock: sha1:e1t2SS9gvkTj6c0UIL+oJwXwL4o= sha1:RxFachY0SXi+jJoWkonySPjp2bg= sha256:ia3Jq5mg9yhfY8cUAtA1r5cTQ/Wd1tBSx2q5VCdeeWI= sha1:PsES3P5HT8GhRiXrdwUH6UtHmko= Xref: csiph.com alt.folklore.computers:234820 John Levine writes: > That was the lesson of the IBM 801. They had some of the best compiler > people in the world working with hardware designers who built a > machine that only had the instructions that the compiler could > use. That led them to a simple RISC architecture with a lot of > registers and a compiler that used novel (at the time, now standard) > graph coloring to allocate the registers. When they retargeted their > PL.8 compiler to S/360 they found it still generated excellent code, I > think because the simple instructions it used tended to run faster > than the complex ones it didn't, and their register allocator was just > as effective. Early last decade, I got asked to track down decision to add virtual memory to all 370. Bascially (os/360) MVT storage management was so bad that REGION sizes frequently had to specified four times larger than used. As result a typical 1mbyte, 370/165 would only run four concurrent regions, throughput insufficient to keep system busy and justified. Going to 16mbyte virtual address space could increase number of concurrent regions by factor of four (capped at 15 because of 4bit storage protect key) with little or no paging (similar to running MVT in CP67 16mbyte virtual machine). I had dropped by Ludlow doing the initial implementation, using 360/67 (pending 370 engineering system with virtual memory). He was doing little bit of code to create virtual memory tables and some simple paging. Biggest issue was EXCP/SVC0 was now being passed channel programs with virtual addresses and channels required real addresses (similar to CP67 running virtual machines), and he borrows CP67 CCWTRANS integrated into One of my hobbies after joining IBM was enhanced production operating systems for internal datacenters (HONE, online branch office sales&marketing support, was one of the 1st and long time customers). With decision to add virtual memory to all 370s, also including doing VM370. In transition of CP67->VM370, lots of stuff was simplified or dropped (including SMP support). I then start adding a lot of stuff back into VM370R2-base, including kernel reorged needed for SMP support (but not full SMP). Then with VM370R3-base, I put lot more stuff back in, including SMP support, originally for HONE so they could upgrade their 158 & 168 systems to 2-CPU (getting twice throughput of single CPU systems). I then get sucked into helping with an effort to do 16-CPU 370 SMP (shared memory multiprocessor) and we con the 3033 processor engineers into helping in their spare time (a lot more interesting that remapping 370/168 logic to 20% faster chips). Everybody thought it was great until somebody tells head of POK (DSD, high-end systems), that it could be decades before the POK favorite son operating system ("MVS") has effective 16-CPU support (MVS docs were that 2-CPU systems were only getting 1.2-1.5 times throughput of 1-CPU; POK doesn't ship 16-CPU system until after turn of century). 1976, there is an "advanced technology" conference in POK where both 801/RISC and 16-processor is presented. One of the 801/RISC people gives me a bad time claiming he had looked at the VM370 product code which had no SMP support. I've observed that it was the last adtech conference until sometime in the 80s (because so many adtech groups were being thrown into the 370 development breach). I had joked that John came up with 801/RISC to be the opposite of the complexity of "Future System". Overlapping transition of 370 to virtual memory the 1st half of the 70s was the "Future System" project, completely different than 370 and was suppose to completely replace 370 (I continued to work on 360&370 all during FS and would periodicall ridicule what they were doing). Internal politics was working on shutting down 370 activities and lack of more new 370 during FS is credited with giving the clone 370 system makers (including Amdahl), their market foothold. When FS finally implodes, there is mad rush getting new stuff into 370 product pipelines, including kicking off quick&dirty 3033&3081 efforts in parallel. Head of POK invites some of us to never visit POK again and directed the 3033 processor engineers, "heads down and no distractions" Part of 801 presentation was PL.8 would only generate correct code and the CP.r operating system would only execute correct PL.8 code. As a result, 801 RISC didn't need hardware protection domains (things like changing address spaces could be done with inline application code). 801 ROMP chip was originally for OPD Displaywriter follow-on. When Displaywriter follow-on was canceled, they decided to pivot to the UNIX workstation market and hired the company that had done PC/IX (for IBM/PC) to do AIX for the PC/RT workstation (but needed ROMP to support UNIX paradigm hardware protection). FS had a lot of object-like characteristics, however one of the last nails in the FS coffin was analysis by IBM Houston Scientific Center that 370/195 apps redone for a FS machine made with the fastest technology available, would have throughput of 370/145 (about 30 times slow down). FS disaster http://www.jfsowa.com/computer/memo125.htm https://en.wikipedia.org/wiki/IBM_Future_Systems_project https://people.computing.clemson.edu/~mark/fs.html ... from "Computer Wars: The Post-IBM World" https://www.amazon.com/Computer-Wars-The-Post-IBM-World/dp/1587981394/ ... and perhaps most damaging, the old culture under Watson Snr and Jr of free and vigorous debate was replaced with *SYNCOPHANCY* and *MAKE NO WAVES* under Opel and Akers. It's claimed that thereafter, IBM lived in the shadow of defeat ... But because of the heavy investment of face by the top management, F/S took years to kill, although its wrong headedness was obvious from the very outset. "For the first time, during F/S, outspoken criticism became politically dangerous," recalls a former top executive ... snip ... Decade after 16-CPU 370 effort, get project to do HA/6000, originally for NYTimes to move their newspaper system (ATEX) off DEC VAXCluster to RS/6000. I rename it HA/CMP https://en.wikipedia.org/wiki/IBM_High_Availability_Cluster_Multiprocessing when I start doing technical/scientific cluster scale-up with national labs (LANL, LLNL, NCAR, etc) and commercial cluster scale-up with RDBMS vendors (Oracle, Sybase, Ingres, Informix) with VAXCluster support in same source base with UNIX. IBM S/88 (relogo'ed Stratus) Product Administrator started taking us around to their customers and also had me write a section for the corporate continuous availability document (it gets pulled when both AS400/Rochester and mainframe/POK complain they couldn't meet requirements). Had coined "disaster survivability" and "geographic survivability" (as counter to disaster/recovery) when out marketing HA/CMP. One of the visits to 1-800 bellcore development showed that S/88 would use a century of downtime in one software upgrade, while HA/CMP had a couple extra "nines" (compared to S/88). One of the first HA/CMP customer installs was new Indian Reservation Casino in Connecticut, was suppose to have week of testing before opening ... but after 24hrs, they decided to open the doors (based on projected revenue; at the time was largest in the US, still one of the largest in the country) https://en.wikipedia.org/wiki/Foxwoods_Resort_Casino#Debt_default Early Jan92, there was HA/CMP meeting with Oracle CEO and IBM/AWD executive Hester tells Ellison that we would have 16-system clusters by mid92 and 128-system clusters by ye92. Mid-jan92, I update FSD on HA/CMP work with national labs and FSD decides to go with HA/CMP for federal supercomputers. By end of Jan, we are told that cluster scale-up is being transferred to Kingston for announce as IBM Supercomputer (technical/scientific *ONLY*) and we aren't allowed to work with anything that has more than four systems (we leave IBM a few months later). A couple weeks later, 17feb1992, Computerworld news ... IBM establishes laboratory to develop parallel systems (pg8) https://archive.org/details/sim_computerworld_1992-02-17_26_7 Some speculation that HA/CMP would have eaten the mainframe in the commercial market. 1993 industry benchmarks (number of program iterations compared to the industry MIPS/BIPS reference platform): ES/9000-982 : 8CPU 408MIPS, (51MIPS/CPU) RS6000/990 (RIOS chipset) : 1-CPU: 126MIPS, 16-systems: 2BIPS, 128-systems: 16BIPS Executive we had reported to, goes over to head up Somerset/AIM (Apple, IBM, Motorola) to do single chip 801/RISC (Power/PC) and uses Motorola 88k bus/cache enabling SMP implementations.= -- virtualization experience starting Jan1968, online at home since Mar1970