Path: csiph.com!news.mixmin.net!eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Anne & Lynn Wheeler Newsgroups: alt.folklore.computers Subject: Re: TOPS-20 Boot Camp for VMS Users 05-Mar-2022 Date: Sat, 24 Dec 2022 14:46:06 -1000 Organization: Wheeler&Wheeler Lines: 33 Message-ID: <871qoonwdt.fsf@localhost> References: <20220303163807.e700772e93bf9d81a0d8646d@eircom.net> <5H6UJ.233887$Rza5.134368@fx47.iad> <1480498945.668113352.883426.peter_flass-yahoo.com@news.eternal-september.org> <87fsnxl8dt.fsf@nightsong.com> <1585529182.668284324.850327.peter_flass-yahoo.com@news.eternal-september.org> <871qopg8qi.fsf@localhost> MIME-Version: 1.0 Content-Type: text/plain Injection-Info: reader01.eternal-september.org; posting-host="371d055dc63f07fb66ea95d87635f7ad"; logging-data="2543447"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/N/oxkwfoa9euRAS6cl2Ey/hpw0KjMDlM=" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.1 (gnu/linux) Cancel-Lock: sha1:jIBJB+xKVV2a4KUhBmox5IWyHUE= sha1:86GkLVgkZgk2dvTJVvOmr2r+zRg= Xref: csiph.com alt.folklore.computers:223256 Charlie Gibbs writes: > After all, MIPS really stands for > "Meaningless Indication of Processor Speed". ... as an aside, IBM mainframe has hyping its faster processor Ghz and no hardware multi-threading ... somehow trying to imply it corresponded to faster instruction execution ... when the mainframe didn't come close to approaching processor power of other platforms i.e. totally lacked out-of-order (and multi-threaded) cache miss compensation until z196 and then only started to evolve the technology. this century articles started to appear that (cache miss) memory latency, when measured in count of processor cycles is comparable to 60s IBM 360 mainframe disk access latency, when measured in count of 360 mainframe processor cycles. The (relatively) huge wait for 360 mainframe for disk I/O was some of the motivation for software multiprogramming and multithreading. This started to appear at the hardware level with caches (and cache misses), with waiting for memory is the modern equivalent to 60s waiting for disk I/O ... giving rise to things like hardware multithreading, out-of-order execution, branch prediction and speculative execution IBM mainframes were very late to this game, while at the same time, they were exhacerbating the memory latency problem with increasing processor Ghz speeds ... emphasizing faster Ghz speeds while discounting industry standard MIPS benchmarks (which had better correlation with actually processor throughput, not physically counting instructions ... but counting program iterations compared to the reference platform). -- virtualization experience starting Jan1968, online at home since Mar1970