Path: csiph.com!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail From: john larkin Newsgroups: sci.electronics.design,comp.arch.fpga Subject: Re: 50 cent DDS synthesizer Date: Sun, 26 Oct 2025 07:56:39 -0700 Organization: A noiseless patient Spider Lines: 106 Message-ID: References: <8fjifkteog2a8s8960dk7lak7kh70lrtta@4ax.com> <10dcmfd$1fcrk$1@dont-email.me> <20251023a@crcomp.net> <10ddo5a$1v5hk$1@dont-email.me> <10df7vg$2dvoi$1@dont-email.me> <10djh8v$2h1af$1@paganini.bofh.team> <10dkl12$3sl8j$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Injection-Date: Sun, 26 Oct 2025 14:56:41 +0000 (UTC) Injection-Info: dont-email.me; posting-host="45419367995ac014478ef4d7a38b3500"; logging-data="89390"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19vESqAZKg3l74c9A0XrYMY" User-Agent: ForteAgent/8.00.32.1272 Cancel-Lock: sha1:gl5c2JTRVc5ONtAF061TD2vHVq4= Xref: csiph.com sci.electronics.design:737151 comp.arch.fpga:38690 On Sun, 26 Oct 2025 08:10:08 GMT, Jan Panteltje wrote: >>antispam@fricas.org (Waldek Hebisch)wrote: >>>In sci.electronics.design Jan Panteltje wrote: >>>>Chris Jones wrote: >>>>>On 24/10/2025 4:20 am, Jan Panteltje wrote: >>>>>> "Don" wrote: >>>>>>> john larkin wrote: >>>>>>> Jan Panteltje wrote: >>>>>>>>> john larkin wrote: >>>>>>>>>> >>>>>>>>> We have a little proto board with a RP2040 Rpi cpu and an Efinix T20 >>>>>>>>> FPGA. The Pi configures the FPGA at powerup and then talks SPI to it. >>>>>>>>> >>>>>>>>> We often need programmable clocks so I added a few parts to make a DDS >>>>>>>>> frequency synthesizer. We use a PLL inside the FPGA to spin up a 204 >>>>>>>>> MHz clock for the 32-bit phase accumulator. The sine lookup is 4K >>>>>>>>> points and the "dac" is six resistors. >>>>>>>>> >>>>>>>>> This lowpass filter is tacky, but it all works. At 50 MHz, the jitter >>>>>>>>> is a few hundred ps p-p, and that looks mostly like amplitude noise to >>>>>>>>> me. >>>>>>>>> >>>>>>>>> https://www.dropbox.com/scl/fo/336qn643xyilkqz5rc9lp/ADC4ThBQa3B-L5auaTDh8fQ?rlkey=q2qrsbdow816id6wgc4eypuas&dl=0 >>>>>>>>> >>>>>>>>> The FPGA 1.2v core supply uses about 30 mA total when this is running >>>>>>>>> at 50 MHz out. >>>>>>>> >>>>>>>> Nice, 250 Ohm is a big load, good the FPGA can handle that. >>>>>>> >>>>>>> The MSB actually sees 500 ohms. >>>>>>> >>>>>>>> >>>>>>>> I was using R2R for video: >>>>>>>> https://www.electronics-tutorials.ws/combination/r-2r-dac.html >>>>>>> >>>>>>> One can buy a real r-2r network cheap, but it's easier to use 0603 >>>>>>> resistors that we have in stock. >>>>>> >>>>>> Also, the ability to adjust assembled resistor values works better for >>>>>> me as a DIYer. Here's mouser's offering for the geniuses in our midst, >>>>>> with the foresight to always choose the correct component: >>>>>> >>>>>> >>>>>> >>>>>> Jan's cited tutorial says: >>>>>> >>>>>> Compared to the R-2R DAC, the binary weighted digital-to-analogue >>>>>> converter has an analogue output voltage which is the weighted >>>>>> sum of the individual inputs. Thus it requires a large range of >>>>>> precision resistors within its ladder network, making its design >>>>>> both expensive and impractical for most DAC's requiring lower >>>>>> levels of resolution. >>>>>> >>>>>> Discussions in this group left me with the impression precision resistor >>>>>> fabrication became trivial thanks to the trimming technology of modern >>>>>> lasers? Is the price of precision resistors still a factor? >>>>> >>>>> In the case of R2R you can use resistors from one batch and that may have less spreading in values >>>>> No precision resistors needed. >>>>> (2R is then 2 1R resistors in series). >>>>> >>>> >>>>You don't want them the same though: The MOSFETS of the CMOS logic >>>>outputs have some on-resistance (maybe 30-50 Ohms) and so the resistors >>>>in series with each of these outputs should be decreased by whatever you >>>>measure that output resistance to be, otherwise the resistance ratio >>>>isn't 1:2 in the R-2R network, and the DNL will be poor. >>>> >>>>You could use the average of the on-resistance of the NMOS and the PMOS >>>>(which are not quite the same), measured on a typical chip, at room >>>>temperature, so that it is usually at least roughly correct, rather than >>>>systematically and always wrong. >>>> >>>>The MOSFET on-resistance is usually a more important effect than the >>>>error of 1% resistor tolerances, so it makes sense to fix that before >>>>worrying about selecting resistors from the same batch. >>>> >>>>It is worth fixing it for R-2R and also for at least a few msbs of >>>>binary weighted resistor DACs. >>> >>> How would you go about measuring MOSFET on resistance? >> >>For logic MOSFETS in IC-s I just used a multimeter. For power >>MOSFETS I used "two meter" method: resitor to limit current to >>reasonable range, ammeter to measure current, voltmeter to >>measure voltage drop on the MOSFET. Actually, I had extrea >>voltmeter to measure gate voltage. > >Yes, that should work. >But in the case of FPGA output there is pull up, pull down, linearity and likely some effects in-between. >But as a simple rule it should work. >Now people here were talking about that IBIS model. >If I ever get spice working on my computers (Raspberries these days) .... >Old spice version could still be running in wine in Linux on old PC upstairs. >For some reason I do not need Spice except in food. Spice is great for playing with ideas. We are developing a series of resistor-inductor simulators, RL dummy loads, that were invented by fiddling with Spice. They work but I still don't understand them. John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics