Path: csiph.com!eternal-september.org!feeder.eternal-september.org!nntp.eternal-september.org!.POSTED!not-for-mail From: Bill Sloman Newsgroups: sci.electronics.design,comp.arch.fpga Subject: Re: fast divider? Date: Mon, 30 Mar 2026 16:42:12 +1100 Organization: A noiseless patient Spider Lines: 108 Message-ID: <10qd2fk$26ddd$1@dont-email.me> References: <189dc18427b8b905$12514$2031059$4006de53@news.newsgroupdirect.com> <6laorktu6oiu397vthkra4ilcdsqdtqpb0@4ax.com> <10plapt$26c7q$6@dont-email.me> <10pmfb0$2gmh7$5@dont-email.me> <10q7psn$atug$5@dont-email.me> <7higskpevth1a4ced39pp3tihtu8dvadi7@4ax.com> <10qab75$171gk$1@dont-email.me> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Injection-Date: Mon, 30 Mar 2026 05:42:14 +0000 (UTC) Injection-Info: dont-email.me; posting-host="78298447f1b60adde5427431e401c2aa"; logging-data="2307501"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19M+5X5TNyjzvCpC5QFSMXb0bydqDrZlf0=" User-Agent: Mozilla Thunderbird Cancel-Lock: sha1:W7zYAxR9cjQZTRvnm7UpdkRmDJo= X-Antivirus: Norton (VPS 260329-6, 30/3/2026), Outbound message In-Reply-To: Content-Language: en-US X-Antivirus-Status: Clean Xref: csiph.com sci.electronics.design:742475 comp.arch.fpga:38721 On 30/03/2026 2:18 am, john larkin wrote: > On Sun, 29 Mar 2026 15:52:53 +1100, Bill Sloman > wrote: > >> On 29/03/2026 8:38 am, john larkin wrote: >>> On Sat, 28 Mar 2026 16:44:40 +1100, Bill Sloman >>> wrote: >>> >>>> On 28/03/2026 5:39 am, john larkin wrote: >>>>> On Sun, 22 Mar 2026 03:00:16 +1100, Bill Sloman >>>>> wrote: >>>>> >>>>>> On 22/03/2026 1:52 am, john larkin wrote: >>>>>>> On Sat, 21 Mar 2026 16:36:43 +1100, Bill Sloman >>>>>>> wrote: >>>>>>> >>>>>>>> On 20/03/2026 4:05 am, john larkin wrote: >>>>>>>>> On Tue, 17 Mar 2026 22:30:01 +0000, someone >>>>>>>>> wrote: >>>>>>>>> >>>>>>>>>> I assume these are up-counters, so the thing overflows at all 1's. Then you only have the one fast carry TPD for the MS18b overflowing to all 1s when a 1 is clocked into its LSB. One whole clock period to clock the 1 out of the DFF and meet the setup times for what I assume is a synchronous LD and its setup for the counters. So that particular timing criticality is a DFF TPD and a LD setup TSU to reliably capture the register data. The LD TPD to CLK TSU for the LS18b counter shouldn't be a problem. This must be very speedy logic for 150MHz. Do you have a simulator that displays how much margin you have on this timing, or is it just a bunch waveforms? >>>>>>>>> >>>>>>>>> Yes, loadable up-counter with carry chain. >>>>>>>>> >>>>>>>>> This would be in an FPGA, so the diagram is just a concept. The >>>>>>>>> reality will be VHDL code. And the FPGA boys use the Wishbone >>>>>>>>> architecture and want the counter to be 32 bits, which is OK with me. >>>>>>>>> >>>>>>>>> We are already doing a DDS at 250 MHz on this chip, an Efinix T20, so >>>>>>>>> I expect we could do a divider in that ballpark. The T20 is in the >>>>>>>>> *slow* Efinix family. >>>>>>>>> >>>>>>>>> I think the T20 has 18-bit fast carry chains. >>>>>>>>> >>>>>>>>> After the boys code this, the tools can verify timing. >>>>>>>>> >>>>>>>>> FPGAs are great, but there's a cultural gap between people who draw >>>>>>>>> and people who type. >>>>>>>> >>>>>>>> Can't say I've noticed that, but since I can do both, and most of the >>>>>>>> engineers I've hung out with could too, John Larkin may be projecting here. >>>>>>> >>>>>>> Gosh Bill, you are wonderful. You are great at everything. >>>>>> >>>>>> I'm certainly not great at writing VHDL. There's a VHDL text-book on my >>>>>> bookshelf - bought for a project which didn't come off - but the stuff I >>>>>> did type was in a much less powerful language, but powerful enough to >>>>>> get the chip to do what I wanted it to. >>>>>> >>>>>>> What are you designing now? >>>>>> >>>>>> Absolutely nothing. I do fish for work from time to time, but at 83 I'm >>>>>> not an attractive employee. >>>>> >>>>> Join one of those maker space things, meet some people, offer to help >>>>> for free, see what happens. >>>> >>>> I'm active on the committee of NSW branch of the IEEE but I don't know >>>> of any maker space things in Sydney. >>> >>> Hey, you could google >>> >>> maker spaces sydney australia >> >> https://makerspaces.com.au/nsw/sydney >> >> So they exist. Leather work and needle work (sewing) are supported. I am >> a tolerably competent carpenter so I might fit in. As a route into >> advanced electronic design it doesn't look promising. > > We have some of that handicraft stuff here, but we have a lot of > people who want to build things that use electronics, and those people > aren't usually very good circuit designers. [1] > > Some of them are actual startups with an idea and some funding. They > go to meetups to pitch their ideas and maybe meet people who could > help. > > Studio 45 near here has an occasional meetup with 500 people, free > food and beer. We might sponsor one. > > We had a cool one at a Rivian facility. I met a photonics consultant > and recommended Phil's book. And listened to yet another pitch for AI > circuit/pcb design. > > There's one coming up in a pier on the SF Bay, an ocean > instrumentetion outfit. That should be fun. > > I do one or two meetups per month and meet lots of Young Things. > > The point is that you could show up, and meet people who need > electronics, and see what happens. If I showed up at the right meetings, I might meet people who needed electronics. The odds don't look great. > Or don't. That would seem to be the rational choice. > [1] It's impressive how few people are good at electronic design. Even more impressive that you seem to think you can make that statement. If you don't think that a classical emitter-coupled monostable can work, your status as a judge of electronic design quality can't be all that high. -- Bill Sloman, Sydney