Path: csiph.com!weretis.net!feeder9.news.weretis.net!panix!.POSTED.spitfire.i.gajendra.net!not-for-mail From: cross@spitfire.i.gajendra.net (Dan Cross) Newsgroups: alt.folklore.computers,openwatcom.users.c_cpp,comp.lang.c Subject: Re: 16:32 far pointers in OpenWatcom C/C++ Date: Fri, 7 Nov 2025 16:54:44 -0000 (UTC) Organization: PANIX Public Access Internet and UNIX, NYC Message-ID: <10el88k$hqi$2@reader2.panix.com> References: <10eda8d$3pd45$1@dont-email.me> <10el4gt$2cb$1@reader2.panix.com> Injection-Date: Fri, 7 Nov 2025 16:54:44 -0000 (UTC) Injection-Info: reader2.panix.com; posting-host="spitfire.i.gajendra.net:166.84.136.80"; logging-data="18258"; mail-complaints-to="abuse@panix.com" X-Newsreader: trn 4.0-test77 (Sep 1, 2010) Originator: cross@spitfire.i.gajendra.net (Dan Cross) Xref: csiph.com alt.folklore.computers:232073 openwatcom.users.c_cpp:3675 comp.lang.c:395123 In article , Scott Lurndal wrote: >cross@spitfire.i.gajendra.net (Dan Cross) writes: >>In article <10eda8d$3pd45$1@dont-email.me>, >>Peter Flass wrote: >>>On 11/4/25 08:20, Scott Lurndal wrote: >>>> Kaz Kylheku <643-408-1753@kylheku.com> writes: >>>>> On 2025-11-03, Peter Flass wrote: >>>>>> On 11/3/25 13:24, Lynn McGuire wrote: >>>>> >>>>> When I saw this subject line, I thought it was some necroposting to >>>>> threads from 1990. >>>>> >>>>> Someone still cared about segmented x86 shit in 2010 (even if 32 bit)? >>>> >>>> There are still people on the internet who swear that the 286 is >>>> better than sliced bread and refuse to recognize that modern >>>> architectures are superior. >>>> >>> >>>I was thinking, are there any segmented architectures today? Most >>>disguise segmentation as a flat address space (e.g. IBM System/370 et.seq.) >> >>x86_64 is still nominally segmented; what "code segment" the >>processor is running in matters, even in long mode. But most of >>the segment data is ignored by hardware (e.g., base and limits) >>in 64-bit mode. > >Minor correction, an update to AMD64 was done back in >the oughts to support some segment limit registers for 64-bit XEN >(and probably for vmware as well). > >See the LMSLE bit in the EFER register for more details. Interesting. AMD-only, not Intel. This is why we can't have nice things. - Dan C.