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| Newsgroups | comp.sys.prime |
|---|---|
| Date | 2023-01-22 22:50 -0800 |
| References | <b659d260-b301-4f6c-bb03-98e014d06459@googlegroups.com> <def2fc1e-9ceb-4ded-b37e-eba4fde8d61en@googlegroups.com> <49e5334d-7585-42cb-a69e-ff871ca771a2n@googlegroups.com> <pdmdnfNiA_1MBHb9nZ2dnUU7-aGdnZ2d@giganews.com> |
| Message-ID | <291de599-97bb-43bc-98c3-e3992f433d11n@googlegroups.com> (permalink) |
| Subject | Re: Prime bitslice processor |
| From | Bob Allison <bobbyallison@gmail.com> |
On Sunday, July 11, 2021 at 9:24:39 PM UTC-4, Dennis Boone wrote: > > Were the P300 and P400 ECL machines? I hadn't thought so. I have the > > P300 microcode manual, and we once had the microcode boards for the P400 > > at Greater Clark County Schools. I remember looking at them, and I'm > > pretty sure that's what I recall was used. > No, pretty sure the first ECL machine was the 9950. > > I have the data sheets for the 54181/74181 ALU in my 1976 (second > > printing) Texas Instruments TTL Data Book. if they're not already > > online somewhere, let me know, I'll scan the pages. > Check http://bitsavers.org/components/ti/_dataBooks/ - I suspect > it's in there. > > De Yes, the 9950 and all 9000s were ECL with the 2900 family of bit-slice chips. There were 6 boards in the CPU: Execute Units E1 & E2, Instruction I-Unit, S-Unit (Cache), CS (Control Store), and MC (Memory Controller). The 6000 series was ECL with custom Prime-designed Motorola MCA 2500 ECL VLSI for the Execution Unit, Instruction/Cache Unit, Control Store, and Memory Controller with multiple designs on each of the 4 boards that made up the CPU. The next ECL CPU (The Lion project) was to be with the MCA 25000 VLSI but that project was canceled after the takeover attempt and the buyout by JH Whitney and DR Holdings. The 5000 series was with custom Prime-designed CMOS from LSI Logic. That project survived the takeover and the 5370 dual CPU was the last machine to ship.
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Prime bitslice processor Jim Wilcoxson <prirun@gmail.com> - 2020-04-24 07:44 -0700
Re: Prime bitslice processor drb@ihatespam.msu.edu (Dennis Boone) - 2020-04-24 11:04 -0500
Re: Prime bitslice processor Bob Allison <bobbyallison@gmail.com> - 2020-10-21 19:12 -0700
Re: Prime bitslice processor Daiyu Hurst <daiyu.hurst@gmail.com> - 2021-07-10 19:55 -0700
Re: Prime bitslice processor drb@ihatespam.msu.edu (Dennis Boone) - 2021-07-11 20:24 -0500
Re: Prime bitslice processor Daiyu Hurst <daiyu.hurst@gmail.com> - 2021-07-13 10:18 -0700
Re: Prime bitslice processor drb@ihatespam.msu.edu (Dennis Boone) - 2021-07-13 20:18 -0500
Re: Prime bitslice processor Bob Allison <bobbyallison@gmail.com> - 2023-01-22 22:50 -0800
Re: Prime bitslice processor Bob Allison <bobbyallison@gmail.com> - 2023-01-22 22:55 -0800
Re: Prime bitslice processor Bob Allison <bobbyallison@gmail.com> - 2023-01-22 23:05 -0800
Re: Prime bitslice processor Daiyu Hurst <daiyu.hurst@gmail.com> - 2023-06-27 11:41 -0700
Re: Prime bitslice processor drb@ihatespam.msu.edu (Dennis Boone) - 2023-06-28 02:01 +0000
Re: Prime bitslice processor drb@ihatespam.msu.edu (Dennis Boone) - 2023-06-28 02:46 +0000
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