Path: csiph.com!v102.xanadu-bbs.net!xanadu-bbs.net!news.glorb.com!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!border4.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail
From: aiiadict@gmail.com
Newsgroups: comp.sys.apple2.programmer
Subject: Re: standard interface to aux RAM or RWIII RAM?
Date: Sat, 12 May 2012 15:31:38 -0700 (PDT)
Organization: http://groups.google.com
Lines: 60
Message-ID: <22743612.1108.1336861898413.JavaMail.geo-discussion-forums@yngr17>
References: <17930098.380.1336698476486.JavaMail.geo-discussion-forums@vbez18> <6385962.1602.1336753916732.JavaMail.geo-discussion-forums@vbjb10> <25746570.216.1336783342741.JavaMail.geo-discussion-forums@vbws2>
NNTP-Posting-Host: 108.230.94.47
Mime-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
X-Trace: posting.google.com 1336862366 1643 127.0.0.1 (12 May 2012 22:39:26 GMT)
X-Complaints-To: groups-abuse@google.com
NNTP-Posting-Date: Sat, 12 May 2012 22:39:26 +0000 (UTC)
In-Reply-To: <25746570.216.1336783342741.JavaMail.geo-discussion-forums@vbws2>
Complaints-To: groups-abuse@google.com
Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=108.230.94.47; posting-account=5kmk9wkAAAB22-WWGK8UTn8vQ5c3EvdQ
User-Agent: G2/1.0
Xref: csiph.com comp.sys.apple2.programmer:298

On Friday, May 11, 2012 5:42:22 PM UTC-7, aiia...@gmail.com wrote:
>=20
> where does this alternate 4K bank of RAM exist at?  in the aux
> bank 0?
>=20


from:=20

http://vinace.sourceforge.net/en-x187.html

"""""""""""""""""""""""""""
8.3.2. Language Card bus

Reference : Apple IIe Technical Reference Manual pages 79 to 83 (PDF pp113-=
117)

Language Card bus is in charge of the upper 12K memory. This space was orig=
inally dedicated to Basic and Monitor ROM in 48K Apple ][. On 64K Apples, a=
 new possibility was to address RAM in this space. This feature is used to =
load alternative languages in memory (like ][+ Integer Basic on a //e).

Read and Write can be switched independently. This allows to write into RAM=
 while ROM is visible. It is quite convenient when setting up the RAM as ma=
ny low level routines are in ROM (text display, keyboard input...).

As there are 16K available RAM but only a 12K slot, the low 4K ($D000-$FFFF=
) can address two banks of RAM. The high 8K are always connected to the sam=
e RAM.

This bus is driven by the Language Card Unit using LCRAM, LCWRITE and LCBNK=
2 soft switches.

By default (LCRAM is off, LCWRITE off), the ROM is readable and write reque=
sts has no effect.

Write requests are forwarded to RAM if LCWRITE is set. If it is not set, wr=
ite requests have no effect (like for ROM).

Read requests are forwarded to RAM if LCRAM is set and to ROM if it is not =
set.

High 8K requests ($E000-$FFFF) are connected to highest 8K of RAM ($E000-$F=
FFF).

Low 4K requests ($D000-$DFFF) are connected to RAM at $D000-$DFFF if LCBNK2=
 is set or to RAM at $C000-$CFFF if not.

"""""""""""""""""""""""""""



Ok, so there are two 4k RAM areas that can be switched into D000...

is this on the motherboard?  on the 80 column card?

Does each aux bank have it's own alternate 4k area for D000?


Rich