Path: csiph.com!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: rbowman Newsgroups: comp.os.linux.misc Subject: Re: ARM 32-bit Linux... Date: 8 Sep 2025 18:19:26 GMT Lines: 39 Message-ID: References: <109hc35$31ut6$1@dont-email.me> <20250906165353.1c4c5725@ryz.dorfdsl.de> <68bcb7f7@news.ausics.net> <109jmsf$3i2d7$11@dont-email.me> <109ktf3$3tta6$5@dont-email.me> <109mdhc$7ige$13@dont-email.me> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Trace: individual.net ma/QRPz+am7F1ZIXd1NZpAoLgFPPpga5v2tJp3TVlHNugDcxCd Cancel-Lock: sha1:MA+wXZDIVDuj3TXibhdljU49PI8= sha256:vY5+4+dSBhV7ZpSyrBFUqYhzQwOxjJ+NJF7jMEHsJuE= User-Agent: Pan/0.162 (Pokrosvk) Xref: csiph.com comp.os.linux.misc:73724 On Mon, 8 Sep 2025 12:09:32 +0100, The Natural Philosopher wrote: > On 07/09/2025 22:48, rbowman wrote: >> On Sun, 7 Sep 2025 21:29:07 -0000 (UTC), Lawrence D’Oliveiro wrote: >> >>> On Sun, 7 Sep 2025 11:30:39 +0100, The Natural Philosopher wrote: >>> >>>> There are far far more ARM chips in the world than Intel ones >>> >>> More ARM chips are made per year than the entire population of the >>> Earth. >>> >>> The same might be true of RISC-V, too. >> >> Do you count th RP2350 as a point for each? > > RP2350 is not RISC-V AFAIK > > Its ARM. It's both. It has two Cortex-M33 ARM cores and two Hazard3 RISC-V cores. Only two can be active at one time, but I've read it can be one ARM and one RISC-V. No idea how you would pull that off. I've got a couple of Pico 2 Ws but haven't done anything with RISC-V. There is a MicroPython uf2 for RISC-V, but that obscures the processor. I don't know if there are limitations between the two. https://micropython.org/download/RPI_PICO2/ I think the C SDK is a similar situation with the build being controlled by CMakeLists.txt, the same as Pico and Pico 2 builds are differentiated. I don't know why they did it other than to prove they could. People who have bench marked it concluded the RISC-V core is slower than the ARM although possibly a little faster than the Pico ARM Cortex-M0+.