Path: csiph.com!eternal-september.org!feeder.eternal-september.org!nntp.eternal-september.org!.POSTED!not-for-mail From: John Ames Newsgroups: comp.os.linux.misc Subject: Re: Memory Safety (Re: Python: A Little Trick For Every Need) Date: Tue, 10 Feb 2026 08:00:35 -0800 Organization: A place where nothing fits quite right Lines: 23 Message-ID: <20260210080035.000048d0@gmail.com> References: <9hlumk1lodkjlm9a6egbo2fa79f85v6mad@4ax.com> <10lqdk2$n03u$1@dont-email.me> <10lrt1t$16vf1$1@dont-email.me> <-EOdnRUZmNTqQx_0nZ2dnZfqn_qdnZ2d@giganews.com> <10m28je$38cir$3@dont-email.me> <10m2bqs$39oes$1@dont-email.me> <10m2qvk$3g6mr$1@dont-email.me> <10m4go5$2gva$3@dont-email.me> <10m7b6c$10ebk$7@dont-email.me> <20260209100449.0000348a@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Injection-Date: Tue, 10 Feb 2026 16:00:40 +0000 (UTC) Injection-Info: dont-email.me; posting-host="4ad7a4bebb1a4fc255b8a2f01b43186c"; logging-data="3960668"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+ENFC6N2Q62noLbZlQe473IO1rBq41bu0=" Cancel-Lock: sha1:ZVo7hvl4Xqria6TfKGKVrqyN4Qs= X-Newsreader: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Xref: csiph.com comp.os.linux.misc:81908 On Mon, 9 Feb 2026 23:39:05 -0500 c186282 wrote: > Alas it's not 'dense' ... ie the chips don't hold THAT much info in > comparison to typical flash. I think you can find 512kb ferro chips, > and that's about it. > > GREAT for lower-end/microcontroller/field devices. But yer not gonna > be buffering video frames. > > Anyway, look on Mouser and DigiKey ... I2C examples are most common > but there do seem to be a few more, maybe faster, options. Actually have a coupla parts hanging around, from the period where it was new enough they'd hand out samples to anyone passing themselves off as a researcher ;) Think I've got a meg or two of the second-generation stuff (and another 64KB of first-gen, but the read/rewrite life on that is specced an order or two of magnitude lower.) Had the notion to use old cache SRAMs as a 1:1 write-through cache to keep wear to a minimum; just haven't gotten around to *doing* it yet. Well, oneathesedays...