Path: csiph.com!x330-a1.tempe.blueboxinc.net!usenet.pasdenom.info!news.albasani.net!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail From: Gregory Ewing Newsgroups: comp.lang.python Subject: Re: Python CPU Date: Tue, 05 Apr 2011 10:05:18 +1200 Lines: 22 Message-ID: <8vutl0Fdm3U1@mid.individual.net> References: <01bd055b-631d-45f0-90a7-229da4a9a362@t19g2000prd.googlegroups.com> <8vps7tF9vuU1@mid.individual.net> <4d97f125$0$29992$c3e8da3$5496439d@news.astraweb.com> <4d981eb5$0$10581$742ec2ed@news.sonic.net> <8vtbclF7q4U1@mid.individual.net> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Trace: individual.net GXQjrnv5FLX5o6m2e2hXpw9ZuvIFIUXBYoiK6I7vqDwNA4n+vy Cancel-Lock: sha1:5LGakDafDJHi75y1ggMSss5bRjU= User-Agent: Mozilla Thunderbird 1.0.5 (Macintosh/20050711) X-Accept-Language: en-us, en In-Reply-To: Xref: x330-a1.tempe.blueboxinc.net comp.lang.python:2604 geremy condra wrote: > I'd be interested in seeing the performance impact of this, although I > wonder if it'd be feasible. A project I have in the back of my mind goes something like this: 1) Design an instruction set for a Python machine and a microcode architecture to support it 2) Write a simulator for it 3) Use the simulator to evaluate how effective it would be if actually implemented, e.g. in an FPGA. And if I get that far: 4) (optional) Get hold of a real FPGA and implement it -- Greg