Path: csiph.com!usenet.pasdenom.info!news.albasani.net!.POSTED!not-for-mail From: Uri Guttman Newsgroups: comp.lang.perl.misc Subject: Re: three computing drawbacks Date: Mon, 22 Jul 2013 03:54:42 -0400 Organization: albasani.net Lines: 40 Message-ID: <87zjtfvxkt.fsf@stemsystems.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: news.albasani.net I3m8ZWmHwxWN1NE1y4WuzjhVjC1gX8UFIfDEHwPhZds27QJ7wmCwASa04G5BRiRpEoHwvBPxwGJBD8UAuNYqtA== NNTP-Posting-Date: Mon, 22 Jul 2013 07:55:17 +0000 (UTC) Injection-Info: news.albasani.net; logging-data="tfwZHWc/pWeESwBc405yjduv8/Mx2TBNIc6meMyPnyggMp80yVeUw7DiwepaDJdDbL5JCFN9vpz5Ozob2aHHy/rjWgoefQSIhHCSBXe3rf0ZMpzSeApgriKP5++IaaFV"; mail-complaints-to="abuse@albasani.net" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.2 (gnu/linux) Cancel-Lock: sha1:og/sAVUsLs5USthmXmooAOzErj8= sha1:Elr0G8tgZkgwEM/8sgKLnOFaSh4= Xref: csiph.com comp.lang.perl.misc:8801 >>>>> "GM" == George Mpouras writes: GM> Not exactly a perl thread. Here are the three drawbacks (I think) GM> that have kept computing back GM> 1) Binary system. For digital processors should be three or four GM> states so with the same hardware everything would be four times GM> faster. been tried. some old russian system had 3 voltage states. much harder to create in general and likely almost impossible on the scale of todays chips. having a transistor go all the way on or off is easy. having a circuit to check the level of voltage accurate is much more complex. also the logic tables are not easily coded for. what are the 'tri-boolean' function results? also you don't get speedup, you gain 'density' but density is very very cheap now. GM> 2) Bytes should have arbitrary length of “tribits” or “tetrabits GM> (Unicode is a definition because of the fixed 8bit bytes) already done. see PDP-10/decsystem 10 or 20. so unusable that a c compiler on a dec 20 i used had to put each char in a 36 bit word. bytes are any size you want on that cpu and sequential access support is built in. random access is very tricky and slow as code has to do it. GM> 3) Clocks. Everything should be absolute asynchronous so the GM> chips/electronic would utilized only when needed. Less energy GM> greedy and faster also done already. it is a known thing that async hw will be faster and use lower power. the problem is with design. sync systems are easier to design with everything being latched at one time. you can isolate sections and such. an async chip is much harder to design and it still needs sync parts to connect to the outside world. any other 'new' ideas that are actually very old?? :) thanx, uri