Path: csiph.com!1.us.feeder.erje.net!feeder.erje.net!news.misty.com!news.iecc.com!.POSTED.news.iecc.com!nerds-end From: Alain Ketterlin Newsgroups: comp.compilers Subject: Re: Is This a Dumb Idea? paralellizing byte codes Date: Sun, 23 Oct 2022 21:29:34 +0200 Organization: =?utf-8?Q?Universit=C3=A9?= de Strasbourg Sender: news@iecc.com Approved: comp.compilers@iecc.com Message-ID: <22-10-059@comp.compilers> References: <22-10-046@comp.compilers> <22-10-048@comp.compilers> <22-10-056@comp.compilers> MIME-Version: 1.0 Content-Type: text/plain Injection-Info: gal.iecc.com; posting-host="news.iecc.com:2001:470:1f07:1126:0:676f:7373:6970"; logging-data="35750"; mail-complaints-to="abuse@iecc.com" Keywords: parallel, interpreter Posted-Date: 23 Oct 2022 21:53:48 EDT X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:3229 anton@mips.complang.tuwien.ac.at (Anton Ertl) writes: > Alain Ketterlin writes: >>I've heard/read several times that byte-code micro-optimizations are not >>worth the trouble. > > Apart from the paper below, which is discussed below, what else? This is not directly related to the paper I mention later. I was talking about optimizing bytecode vs. compiler optimizations. I know of no interpreter doing elaborate static byte-code optimization. >>https://ieeexplore.ieee.org/document/7054191 > On that I can only say: Not all research papers are trustworthy. > Catchy titles may be a warning signal. > > I did my own measurements on a Haswell (the same CPU they used in the > paper) and published them in > <2015Sep7.142507@mips.complang.tuwien.ac.at> > ( for those of you who > don't know what to do with Message-IDs). [...] > |Why are the results here different from those in the paper? > |1) Different Interpreter 2) different benchmarks. I'm glad it works for you. For the record: they consider interpreters for Python, Javascript and CLI, on a fairly broad set of benchmarks. And they also evaluate (through simulation) branch-predictors that may (or may not) be included in more recent architectures. -- Alain.