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Re: Assembling span-dependent instructions

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On 2022-07-28, antispam@math.uni.wroc.pl <antispam@math.uni.wroc.pl> wrote:
> In comp.arch Kaz Kylheku <480-992-1380@kylheku.com> wrote:
>> On 2022-07-27, Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
>> > However, one can also construct cases where making the code larger can
>> > reduce the minimum size of the immediate operand, e.g.:
>> >
>> > foo:
>> >      movl foo+133-bar(%rdi),%eax
>> > bar:
>>
>> That's weird; what is accessed this way, relative to the code,
>> and does it occur in compiler output?
>
> Code like this may appear due to alignment, say jump to page or cache
> line boundary. In realistic situation one is faced in much more
> compilex problem. Namely on many architectures best way to provide
> constant arguments is by storing constants in memory. This leads to
> "constant pools" and problem where to place them. One wants constant
> pools as close as possible to code, to use short offsets accessing
> them. But for performance reasons it is desirable to put constants in
> separate cache lines. Also, one needs jumps to jump around constant
> pools. Some jumps occur naturally in program, it is good to re-use
> them. But there are possible unused parts of cache lines (both for
> code and constant pools). So there is need to balance loss due to
> unused parts of cache lines (probably dominant factor), length of
> instructions and possible overhead due to extra instructions.

OK; so that makes sense. Say we have a program segment with
some PC relative references to a cache-aligned constant pool
which is farther down the program.

If this program segment shrinks, while the cache-aligned
constant pool stays where it is (to remain aligned),
then that pool will be farther away from some of those
instructions.

This could even happen due to smaller alignments like 8 bytes.
Some instruction loses 4 bytes; then another one experiences
the data being 4 bytes farther than before, which now
doesn't fit.

> There is extra complication when machine has limited range of offsets
> which can be used in single intstruction: when needed offset exceeds
> allowed range one has to change to indirect form which needs free
> register. So there is extra interaction with registes allocation.

On an architecture that is not so register starved, you just
dedicate a register for that. MIPS calls it "at" ("assembler temporary").

--
TXR Programming Language: http://nongnu.org/txr
Cygnal: Cygwin Native Application Library: http://kylheku.com/cygnal

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Assembling span-dependent instructions anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2022-07-27 16:32 +0000
  Re: Assembling span-dependent instructions Kaz Kylheku <480-992-1380@kylheku.com> - 2022-07-27 22:52 +0000
    Re: Assembling span-dependent instructions anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2022-07-28 05:56 +0000
    Re: Assembling span-dependent instructions antispam@math.uni.wroc.pl - 2022-07-28 12:15 +0000
      Re: Assembling span-dependent instructions gah4 <gah4@u.washington.edu> - 2022-07-29 14:22 -0700
      Re: Assembling span-dependent instructions Kaz Kylheku <480-992-1380@kylheku.com> - 2022-07-29 22:36 +0000
  RE: Assembling span-dependent instructions Christopher F Clark <christopher.f.clark@compiler-resources.com> - 2022-07-28 16:02 +0300
    RE: Assembling span-dependent instructions anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2022-07-30 09:28 +0000
      RE: Assembling span-dependent instructions Christopher F Clark <christopher.f.clark@compiler-resources.com> - 2022-07-31 02:28 +0300

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