Path: csiph.com!xmission!news.alt.net!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!news.iecc.com!.POSTED.news.iecc.com!nerds-end From: Bo Persson Newsgroups: comp.compilers Subject: Re: Nitty-gritty aspects of register allocation Date: Fri, 11 Sep 2020 11:44:08 +0200 Organization: Compilers Central Lines: 20 Sender: news@iecc.com Approved: comp.compilers@iecc.com Message-ID: <20-09-030@comp.compilers> References: <20-09-028@comp.compilers> <20-09-029@comp.compilers> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Injection-Info: gal.iecc.com; posting-host="news.iecc.com:2001:470:1f07:1126:0:676f:7373:6970"; logging-data="86336"; mail-complaints-to="abuse@iecc.com" Keywords: optimize, architecture Posted-Date: 11 Sep 2020 22:48:26 EDT X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: csiph.com comp.compilers:2601 On 2020-09-11 at 03:01, Alexei A. Frounze wrote: > On Thursday, September 10, 2020 at 5:14:12 PM UTC-7, Elijah Stone wrote: >> - The second-lowest 8 bits of some registers can be addressed >> separately. When does it make sense to use them? > > AFAIR, on modern CPUs there are penalties in using subregisters. > See e.g. Agner Fog's optimization manuals for details. > A long time ago, when translating 8085 code to 8086 - and mapping a pair of 8-bit registers onto a 16-bit register - it was an advantage to have separate access to the two halves. Nowadays you just don't do that, so when more registers were added this feature was not propagated to those. That's why these instructions are only available for some registers. Bo Persson