Path: csiph.com!x330-a1.tempe.blueboxinc.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!border3.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!news.iecc.com!lnews.iecc.com!nerds-end From: amker Newsgroups: comp.compilers Subject: Re: How to eliminate redundant constant move instructions Date: Tue, 1 Nov 2011 21:04:24 -0700 (PDT) Organization: Compilers Central Lines: 36 Sender: news@iecc.com Approved: comp.compilers@iecc.com Message-ID: <11-11-011@comp.compilers> References: <11-10-019@comp.compilers> <11-11-004@comp.compilers> <11-11-005@comp.compilers> NNTP-Posting-Host: lnews.iecc.com X-Trace: gal.iecc.com 1320288081 6065 64.57.183.34 (3 Nov 2011 02:41:21 GMT) X-Complaints-To: abuse@iecc.com NNTP-Posting-Date: Thu, 3 Nov 2011 02:41:21 +0000 (UTC) Keywords: optimize Posted-Date: 02 Nov 2011 22:41:21 EDT X-submission-address: compilers@iecc.com X-moderator-address: compilers-request@iecc.com X-FAQ-and-archives: http://compilers.iecc.com Xref: x330-a1.tempe.blueboxinc.net comp.compilers:313 On Nov 2, 6:35 am, glen herrmannsfeldt wrote: > That is what register renaming is for. Usually using more than > the architecturally specified number of registers, the CPU > internally remaps the registers such that it can keep one value > in a register while an instruction is being executed out of order. For this specific case, I previous intention was optimizing codes rx <- 0 ... use rx ... ry <- 0 use ry into rx <- 0 ... use rx ... use rx In this manner, I guess the register renaming won't help, since the transformation introduces true dependency, right? > Now, how to choose the > weights when one doesn't know the specific target processor? > That is a good question. How could this happen if middle end does not know the specific processor? What I can image is there should be a way in which back end provides information. Thanks