optimizing

Path	csiph.com!x330-a1.tempe.blueboxinc.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!news.glorb.com!usenet.stanford.edu!usenet.osg.ufl.edu!news.lightlink.com!news.iecc.com!nerds-end
From	glen herrmannsfeldt <gah@ugcs.caltech.edu>
Newsgroups	comp.compilers
Subject	optimizing
Date	Fri, 12 Aug 2011 04:05:54 +0000 (UTC)
Organization	Aioe.org NNTP Server
Lines	31
Sender	news@iecc.com
Approved	comp.compilers@iecc.com
Message-ID	<11-08-015@comp.compilers> (permalink)
NNTP-Posting-Host	news.iecc.com
X-Trace	gal.iecc.com 1313202004 87401 64.57.183.58 (13 Aug 2011 02:20:04 GMT)
X-Complaints-To	abuse@iecc.com
NNTP-Posting-Date	Sat, 13 Aug 2011 02:20:04 +0000 (UTC)
Keywords	optimize, question
Posted-Date	12 Aug 2011 22:20:04 EDT
X-submission-address	compilers@iecc.com
X-moderator-address	compilers-request@iecc.com
X-FAQ-and-archives	http://compilers.iecc.com
Xref	x330-a1.tempe.blueboxinc.net comp.compilers:232

Show key headers only | View raw

A recent post to comp.lang.fortran on optimization reminded me of
something I thought about some time ago.  Someone was wondering if any
optimization was done at link time.  In the case of Fortran, the
answer is usually no.

It seems to me, though, that in the case of RISC, and even more in the
case of VLIW processors like Itanium, delaying the final optimization
and code generation pass would be useful.

For processors which depend on the compiler to generate optimal code
sequences (that is, ones that don't do out-of-order execution) and
assuming that you want to allow for improved versions of the
processor, delaying code generation would be very useful.

It could be done at run time, or, more likely, at program install
time.  (The latter limits the ability to move a disk between systems,
but that shouldn't be so much of a problem.)

One possibility would be to supply the optimization and code
generation either as an on-chip ROM, or a separate ROM that come
with the processor.  Also, the intermediate code format has to
be standardized well enough to allow for it.

Though this requires compiler designers and processor designers
to talk to each other, which might not happen as often as it should.

-- glen
[This is pretty standard in the toolchains for embedded processors.  I
gather that the ARM compilers generate intermediate code, and all the
optimization and code generation happens in the linker. -John]

Back to comp.compilers | Previous | Next — Next in thread | Find similar

Thread

optimizing glen herrmannsfeldt <gah@ugcs.caltech.edu> - 2011-08-12 04:05 +0000
  Re: optimizing anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2011-08-13 12:38 +0000
  Re: optimizing Hans Aberg <haberg-news@telia.com> - 2011-08-13 18:12 +0200
    Re: optimizing Volker Birk <bumens@dingens.org> - 2011-08-15 13:16 +0000
      Re: optimizing Hans Aberg <haberg-news@telia.com> - 2011-08-15 18:55 +0200
  Re: optimizing Walter Banks <walter@bytecraft.com> - 2011-08-14 06:29 -0400
    Re: optimizing glen herrmannsfeldt <gah@ugcs.caltech.edu> - 2011-08-15 18:03 +0000
  Re: optimizing torbenm@diku.dk (Torben Ægidius Mogensen) - 2011-08-15 09:39 +0200

csiph-web