Path: csiph.com!x330-a1.tempe.blueboxinc.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!news.glorb.com!usenet.stanford.edu!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail From: MitchAlsup Newsgroups: comp.arch Subject: Re: Single Thread Performance Date: Tue, 7 Feb 2012 16:00:28 -0800 (PST) Organization: http://groups.google.com Lines: 20 Message-ID: <9164712.4469.1328659228862.JavaMail.geo-discussion-forums@vbbfd4> References: <1083982.844.1328506553065.JavaMail.geo-discussion-forums@vbtr6> Reply-To: comp.arch@googlegroups.com NNTP-Posting-Host: 72.177.28.22 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 X-Trace: posting.google.com 1328659664 1464 127.0.0.1 (8 Feb 2012 00:07:44 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Wed, 8 Feb 2012 00:07:44 +0000 (UTC) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=72.177.28.22; posting-account=H_G_JQkAAADS6onOMb-dqvUozKse7mcM User-Agent: G2/1.0 X-Google-Web-Client: true Xref: x330-a1.tempe.blueboxinc.net comp.arch:5809 On Tuesday, February 7, 2012 11:38:32 AM UTC-6, Tim McCaffrey wrote: > I seem to remember you quoting similar numbers for 32 vs 16 registers, I quote this as 3%-ish (compiled code) > and 3 operand vs 2 operand ISAs. Don't remember ever quoting a delta here. > So, design an ISA with 32 registers, 3 operand opcodes that is just as code > dense as an x86 (for I-Cache efficiency), Don't know if any RISC encoding ever got this close to x86 code density. > double the area, cost and power and > you might get anywhere from 15-50% performance increase. Given a several-wide x86 machine (like say an Opteron) in an already advanced process (like say Intel FABs): I you can double the power budget, you can probably get 10% more ILP and probably 30% more frequency. Mitch