Path: csiph.com!x330-a1.tempe.blueboxinc.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!newsfeed.hal-mli.net!feeder1.hal-mli.net!border3.nntp.dca.giganews.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local2.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Sat, 04 Feb 2012 00:49:31 -0600 Message-ID: <4F2CD4FA.4050004@SPAM.comp-arch.net> Date: Fri, 03 Feb 2012 22:49:30 -0800 From: "Andy (Super) Glew" Reply-To: andy@SPAM.comp-arch.net Organization: comp-arch.net User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:9.0) Gecko/20111222 Thunderbird/9.0.1 MIME-Version: 1.0 Newsgroups: comp.arch Subject: Re: M68k add to memory is not a mistake any more References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com X-Trace: sv3-1jfsBnAEAAFoVXg/4uY3B658P+6eQcc19nGgQLioKURyup7QaqVyhBsKjk77FHC0Mp2y2R3W+aqS7Fe!45KDH8Q3M5fTCrM23OV5hNO43h81cOJpDQNLpWFPeOipIhqd1Q+gVXBRuzHxFRU= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.40 X-Original-Bytes: 2564 Xref: x330-a1.tempe.blueboxinc.net comp.arch:5696 On 2/3/2012 10:14 PM, Stephen Sprunk wrote: > On 03-Feb-12 00:42, Terje Mathisen wrote: >> Stephen Sprunk wrote: >>> I'm a fan of load/store architectures and dislike mem-op-mem (and >>> mem-op, for that matter) instructions in general, but the latter seem to >>> be back in favor these days due to higher code density and therefore >>> higher utilization of decode bandwidth. >> >> I do like mem-op, even if I've been conditioned (by the 486 and Pentium) >> to avoid them and instead manually schedule the load part to happen as >> early as possible. > > Of course, with a larger register set and no mem-op instructions, it > would have been much easier for compilers to do load hoisting as well, > not to mention much lower stack pressure due to x86's limited register set. > > I wonder if x86 could have gone another generation or two without OoO if > it hadn't become necessary so soon for the CPU to crack mem-op > instructions and do its own load hoisting. That transistor budget could > have, instead, gone into wider execution and/or larger caches. Possibly. However, I think it is worth noting that OoO P6 x86 is really the Intel chip that killed the RISC upstarts. All of the competitors could have played the same games.