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| From | Nioclás Pól Caileán de Ghloucester <Master_Fontaine_is_dishonest@Strand_in_London.Gov.UK> |
|---|---|
| Newsgroups | comp.lang.vhdl, comp.arch.fpga, comp.arch.embedded |
| Subject | Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers |
| Date | 2024-08-07 20:51 +0200 |
| Organization | A noiseless patient Spider |
| Message-ID | <584da9c2-ae9d-42a6-1bc9-e29b36aab0f3@Strand_in_London.Gov.UK> (permalink) |
| References | <5ccd7c07-93d6-424d-909b-b13ebe6cf1f2n@googlegroups.com> <8fd3081d-4977-c809-2c81-c200605ac323@insomnia247.nl> <v8usi3$26hka$1@dont-email.me> |
Cross-posted to 3 groups.
On Tue, 6 Aug 2024, Fereydoun Memarzanjany wrote: "[. . .] I'll respond to them now." Welcome back!
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Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Nioclás Pól Caileán de Ghloucester <Master_Fontaine_is_dishonest@Strand_in_London.Gov.UK> - 2024-07-21 18:16 +0200
Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Buzz McCool <buzz_mccool@yahoo.com> - 2024-08-01 12:17 -0700
Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Fereydoun Memarzanjany <thraetaona@ieee.org> - 2024-08-06 22:24 -0600
Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Fereydoun Memarzanjany <thraetaona@ieee.org> - 2024-08-06 22:18 -0600
Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers Nioclás Pól Caileán de Ghloucester <Master_Fontaine_is_dishonest@Strand_in_London.Gov.UK> - 2024-08-07 20:51 +0200
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