X-Received: by 10.36.117.83 with SMTP id y80mr1208696itc.48.1510328137353; Fri, 10 Nov 2017 07:35:37 -0800 (PST) X-Received: by 10.157.1.161 with SMTP id e30mr388291ote.2.1510328137132; Fri, 10 Nov 2017 07:35:37 -0800 (PST) Path: csiph.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!l196no90785itl.0!news-out.google.com!193ni3063iti.0!nntp.google.com!186no86241itu.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.arch.fpga Date: Fri, 10 Nov 2017 07:35:36 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=68.44.229.196; posting-account=BcpLkAoAAACbVwkzAAKP0XXOd-MDREpp NNTP-Posting-Host: 68.44.229.196 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <2f3344b5-c9b4-4cee-bbf9-bd96efb89497@googlegroups.com> Subject: FPGA motherboard for 80386 CPU From: "Rick C. Hodgin" Injection-Date: Fri, 10 Nov 2017 15:35:37 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 53 Xref: csiph.com comp.arch.fpga:10516 The 80386DX CPU had 132 pins: 80386DX and 80386SX pinouts: http://www.rfwireless-world.com/images/80386-pin-diagram.jpg https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884 General architecture: http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf Of these pins on the DX variant: 32 pins -- data 30 pins -- address 4 pins -- byte enables in 32-bit writes 1 pin -- Read/write 1 pin -- Data/Control 1 pin -- Memory/IO 1 pin -- Bus mastering lock issued by CPU 1 pin -- Bus16 size (16-bit when asserted, normally 32-bit) 1 pin -- Next address (for pipelining) 1 pin -- Address valid signal -- 73 pins -- For basic I/O 3 pins -- Math-coprocessor support 1 pin -- Ready (or Wait, for bus cycles to complete) 2 pins -- Hold and Hold Acknowledge (for bus mastering) 2 pins -- Interrupt and Non-masktable Interrupt -- 8 pins -- General coordination with external peripherals 1 pin -- Reset 1 pin -- Double-pumped clock -- 2 pins -- System input The rest of the pins are unused, go to VSS or VCC. This means that for a full 80386 "motherboard" only 83 pins are required to fully support its operation, 67 of which are address, data, and data type, leaving really only 15 pins of complex operation for a state machine. ----- Would anybody be able to help me create this 80386 motherboard using an AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would like to get it working with a single-step operation for design validation, and then to begin ramping it up. I figure I'll have an area of ROM which the CPU boots to load, which is a tiny real mode program, which begins computing something that can be exam- ined by the FPGA to test successful operation. And then move on to more complex operations, including a custom microkernel. -- Rick C. Hodgin