X-Received: by 10.36.112.2 with SMTP id f2mr15153572itc.36.1514153056347; Sun, 24 Dec 2017 14:04:16 -0800 (PST) X-Received: by 10.157.82.148 with SMTP id f20mr942180oth.2.1514153056146; Sun, 24 Dec 2017 14:04:16 -0800 (PST) Path: csiph.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!g80no2257761itg.0!news-out.google.com!b73ni7992ita.0!nntp.google.com!g80no2257756itg.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.arch.fpga Date: Sun, 24 Dec 2017 14:04:15 -0800 (PST) In-Reply-To: <_lh%B.20537$la6.5097@fx24.iad> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:800:c002:abc2:d57a:29a9:fb8:5f6c; posting-account=BcpLkAoAAACbVwkzAAKP0XXOd-MDREpp NNTP-Posting-Host: 2601:800:c002:abc2:d57a:29a9:fb8:5f6c References: <2f3344b5-c9b4-4cee-bbf9-bd96efb89497@googlegroups.com> <9d1a9600-7ce0-46d0-bcf8-7b208ef15f48@googlegroups.com> <4e4308d8-55d2-45e6-b089-32e9793f5c51@googlegroups.com> <60cd11d9-0fba-4ee2-9d5d-2efcc6eb48e0@googlegroups.com> <3996b47e-45b6-4e27-abc1-c3c40df6531e@googlegroups.com> <31d1562a-7fb3-4d92-ade4-14f5a4a1f203@googlegroups.com> <97cd983a-cd21-4b5f-b333-5b65a9184830@googlegroups.com> <9900e813-1b45-415d-a8ad-5b1afa16d773@googlegroups.com> <_lh%B.20537$la6.5097@fx24.iad> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <08174fe3-1cfc-4dfd-8a9b-e7696ab2ae2e@googlegroups.com> Subject: Re: FPGA motherboard for 80386 CPU From: "Rick C. Hodgin" Injection-Date: Sun, 24 Dec 2017 22:04:16 +0000 Content-Type: text/plain; charset="UTF-8" Lines: 63 Xref: csiph.com comp.arch.fpga:10609 On Friday, December 22, 2017 at 7:23:27 PM UTC-5, Richard Damon wrote: > On 12/21/17 4:33 AM, Rick C. Hodgin wrote: > > I came across this toolset from ARM recently. > > The Tool in the video is NOT from ARM, but is the Xilinx FPGA tool, and > since some of their FPGAs include a hard core embedded ARM (actually 2), > and others can create cores within the fabric, the tool provides a good > environment for building systems around ARM cores, so you cal learn the > protocols in the cores. There are also a number of peripheral cores > provided to interface with the processor core provided. > > Most of the major FPGA manufactures (at least those with FPGAs big > enough to have a processor core) have similar pieces in their tools. I saw it on the ARM video linked below. My apologies for mis-ascribing it. It's part of their ARM Education Media program. I have never used Xilinx FPGAs. Only Lattice and . > > This is almost exactly what I envisioned Logician's interface > > looking like at 2:15: > > https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m15s > > > > Specifically here at 2:36: > > https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m36s > > > > The drag-and-drop / "connect noodles" approach is what I > > envisioned from Blender. So, this tool has almost exactly > > what I'm looking for. > > > > Except ... I do not like seeing outputs like these at 1:32: > > https://www.youtube.com/watch?v=n9cUiEdqdJU&t=1m32s > > How else do you want to present the state of signals changing over > time? As in the 6502 simulation, with the ability to then graph the outputs in the standard form, but I want to see things by value, by logical port, by time, by change. > > The idea is: I work in direct models of hardware units, and > > the tool generates the required source code for me. > > > > This sort of interface has been around for what, maybe 30 years or more > (I used a similar graphical interface in the mid 80's for designing > parts of FPGAs). > > These tools generally allow you to mix representations over layers, a > block in the graphical form can underneath be another graphical sheet, > or a textual module. And textual module can reference other textual > modules or graphical modules (actually, under the hood, the system > parses the graphical design and creates a textual module that get passed > to the synthesis program). I have seen a couple in the Quartus tool and Lattice has something that is GUI-based, but they are not quite on the same level of use as the one show in the ARM video. I may be reading more into the ARM video presentation than actually exists as I have had a vision in my mind of what I want Logician to look like, and may be projecting that vision onto the Xilinx tools. -- Rick C. Hodgin