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From: kishor <kiishor@gmail.com>
Newsgroups: comp.arch.embedded
Subject: Re: Floating point vs fixed arithmetics (signed 64-bit)
Date: Tue, 27 Mar 2012 04:59:22 -0700 (PDT)
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Sorry for late reply,

I have experimented few things,

1. Signed 32-bit divide by constant of 2^n
     Compiler uses 2 ASR (Arithmetic shift right) & 1 ADD instruction instead of SDIV instruction

2. Signed 32-bit divide by  constant other than 2^n
    It uses SMLAL (signed multiply & accumulate long) & other instructions

3. Unsigned 64-bit divide by constant of 2^n
    It uses 2 LSR & 1 ORR instruction.

4. Unsigned 64-bit divide by constant other than 2^n
5. Signed 64-bit divide by constant of 2^n
6. Signed 64-bit divide by  constant other than 2^n

  It calls __aeabi_ldivmod, __aeabi_uldivmod functions 

I have two queries,

1. Is hardware DIV / SDIV instructions are slower than shift logic?
2. Is it possible to generate shift based logic to case 5 mentioned above?
(Signed 64-bit divide by constant of 2^n)

Thanks,
Kishore.