Path: csiph.com!weretis.net!feeder9.news.weretis.net!panix!.POSTED.localhost!not-for-mail From: Grant Edwards Newsgroups: comp.arch.embedded Subject: Re: arm-gcc, Cortex-M0+, uint64_t and alignment Date: Wed, 21 Jan 2026 03:38:29 -0000 (UTC) Organization: PANIX Public Access Internet and UNIX, NYC Message-ID: <10kphnl$gvp$1@reader2.panix.com> References: <10kns7l$1733k$1@dont-email.me> <10ko98i$1bptj$1@dont-email.me> <10kob7m$qel$1@reader2.panix.com> <10koep6$1dlne$1@dont-email.me> <10kogeb$n48$1@reader2.panix.com> <10kos8h$1ivol$2@dont-email.me> Injection-Date: Wed, 21 Jan 2026 03:38:29 -0000 (UTC) Injection-Info: reader2.panix.com; posting-host="localhost:::1"; logging-data="17401"; mail-complaints-to="abuse@panix.com" User-Agent: slrn/1.0.3 (Linux) Xref: csiph.com comp.arch.embedded:32472 On 2026-01-20, David Brown wrote: > (As an aside, I find it annoying that STRD can be interrupted in the > middle - it means you don't have an atomic 64-bit store. LDRD can also > be interrupted in the middle, but as it is restarted, it gives you a > 64-bit atomic read.) Yes, I just noticed that in the manual the other day, and it seemed like an odd decision. -- Grant