Path: csiph.com!weretis.net!feeder9.news.weretis.net!panix!.POSTED.localhost!not-for-mail From: Grant Edwards Newsgroups: comp.arch.embedded Subject: Re: arm-gcc, Cortex-M0+, uint64_t and alignment Date: Tue, 20 Jan 2026 18:10:19 -0000 (UTC) Organization: PANIX Public Access Internet and UNIX, NYC Message-ID: <10kogeb$n48$1@reader2.panix.com> References: <10kns7l$1733k$1@dont-email.me> <10ko98i$1bptj$1@dont-email.me> <10kob7m$qel$1@reader2.panix.com> <10koep6$1dlne$1@dont-email.me> Injection-Date: Tue, 20 Jan 2026 18:10:19 -0000 (UTC) Injection-Info: reader2.panix.com; posting-host="localhost:::1"; logging-data="23688"; mail-complaints-to="abuse@panix.com" User-Agent: slrn/1.0.3 (Linux) Xref: csiph.com comp.arch.embedded:32469 On 2026-01-20, David Brown wrote: > Cortex M3 and bigger all handle misaligned accesses without problem > (albeit possibly at a performance penalty). FWIW, the M3 can be configured to generate a fault on unaligned accesses, so whether it works or not depends on your low-level init code. I believe that unaligned-fault-enable feature is disabled by default at reset. Also, The M3 only supports non-world aligned accesses for normal signle store/load instructions. LDM/STM and LDRD/STRD will fault on non-word aligned access. -- Grant