Path: csiph.com!weretis.net!feeder8.news.weretis.net!eternal-september.org!reader01.eternal-september.org!.POSTED!not-for-mail From: Anne & Lynn Wheeler Newsgroups: alt.folklore.computers Subject: Re: do some Americans write their 1's in this way ? Date: Tue, 15 Nov 2022 08:42:42 -1000 Organization: Wheeler&Wheeler Lines: 41 Message-ID: <87pmdof49p.fsf@localhost> References: <09gamht0auug1rgkn2ou86aj9p3idjn0ql@4ax.com> <990d8823-8a11-4f01-bb28-fce4d2801cbcn@googlegroups.com> <93ufmhhbcjshvvmck0e34plpdoe8bvppqc@4ax.com> <20221106181827.4e35837e0e4bcb2f66e86b21@127.0.0.1> <7cjlmhdnku47to9m0i3420ajega1fmhn6b@4ax.com> <802387664.689691586.888786.peter_flass-yahoo.com@news.eternal-september.org> <71662817.689779850.928131.peter_flass-yahoo.com@news.eternal-september.org> <927358844.689954656.439593.peter_flass-yahoo.com@news.eternal-september.org> <1981072631.690151705.598930.peter_flass-yahoo.com@news.eternal-september.org> MIME-Version: 1.0 Content-Type: text/plain Injection-Info: reader01.eternal-september.org; posting-host="53eed0884857f786312fc358d0703eb4"; logging-data="2235212"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/ve9eJz846yLnswnd30fxqVufOsQpODc8=" User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.1 (gnu/linux) Cancel-Lock: sha1:I2ogYWn1qGHCNqlqs20p8DQ/omY= sha1:XJTD5Byj1QFQJUSLsQ+8uY2saOg= Xref: csiph.com alt.folklore.computers:222688 Peter Flass writes: > I think most do these days. IBM mainframe memory corrects (IIRC) single-bit > errors and detects multiple-bit errors. more than that for some time, from archived 6sep2001 afc post, 3090 (mid/late 80s) had 64/80 ECC memory, detect (up to) all 16bit errors and correct (up to) all 15bit errors http://www.garlic.com/~lynn/2001j.html#13 other trivia: after joining IBM, I got asked to help with 370/195 hyperthreading ... hypertreading mention in this post about end of acs/360 https://people.cs.clemson.edu/~mark/acs_end.html 195 out-of-order, but no branch-prediction and speculative execution, so conditional branches drained pipeline ... and most codes ran at half 195 rated speed. simulating multiprocessor with two i-streams (running at half rated speed) could keep execution units busy ... modulo MVT/MVS claimed two-processor was 1.2-1.5 throughput of single processor (because of multiprocessor software overhead and lock contention). they also said that big difference between 360/195 and 370/195 (in addition to the few new instructions) was adding 370 hardware instruction retry ... 195 had so many circuits that mean-time between a system transient hardware error was a few hrs. project was canceled when decision was made to add virtual memory to all 370s (and it wasn't justified to do it for 195). trivia: decade ago, i was asked if I could track down the virtual memory decision ... archived afc post from decade ago http://www.garlic.com/~lynn/2011d.html#73 ... basically MVT storage management was so bad that regions had to be specified four times larger than actually used ... result was 1mbyte 370/165 typically only running four concurrent executing regions ... not sufficient to keep it busy/justified. Going to virtual memory would allow number of concurrent regions to be increased by four times with little or no paging. -- virtualization experience starting Jan1968, online at home since Mar1970